summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2025-09-12 13:37:32 +1000
committerDave Airlie <airlied@redhat.com>2025-09-12 13:37:41 +1000
commitcf99b26d3081b1f9961cc213415867706d19a414 (patch)
tree297925ddee936e6e956138cccc530c204a7f8a83 /drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
parent8d04ea1a92b843890b874551959a9b21bc7f30d4 (diff)
parent2fd653b9bb5aacec5d4c421ab290905898fe85a2 (diff)
Merge tag 'amd-drm-next-6.18-2025-09-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.18-2025-09-09: amdgpu: - Add CRIU support for gem objects - SI UVD fix - SI DPM fixes - Misc code cleanups - RAS updates - GPUVM debugfs fixes - Cyan Skillfish updates - UserQ updates - OEM i2c fix - SMU 13.0.x updates - DPCD probe quirk fix - Make vbios build number available in sysfs - HDCP updates - Brightness curve fixes - eDP updates - Vblank fixes - DCN 3.5 PG fix - PBN calcution fix amdkfd: - Add CRIU support for gem objects - Flexible array fix - P2P topology fix - APU memlimit fixes - Misc code cleanups UAPI: - Add CRIU support for gem objects Proposed userspace: https://github.com/checkpoint-restore/criu/pull/2613 radeon: - Use dev_warn_once() in CS parsers Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250909161928.942785-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c')
-rw-r--r--drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
index 42efe838fa85..2d2d2d5e6763 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
@@ -66,6 +66,13 @@ u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
(amdgpu_crtc->v_border * 2));
vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
+
+ /* we have issues with mclk switching with
+ * refresh rates over 120 hz on the non-DC code.
+ */
+ if (drm_mode_vrefresh(&amdgpu_crtc->hw_mode) > 120)
+ vblank_time_us = 0;
+
break;
}
}