diff options
| author | Mukul Joshi <mukul.joshi@amd.com> | 2025-04-24 21:51:23 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-08 13:56:35 -0500 |
| commit | db29ddf6505f3e831e000c95ae013b18a37f70bc (patch) | |
| tree | d46e9fa8c2379f92bedade047977bf39a16a37b9 /drivers/gpu/drm/amd | |
| parent | 5056b75fedc01de0563267c53e1aa7e41357f37a (diff) | |
drm/amdgpu: Add per-ASIC PTE init flag
On GFX12.1, default PTE setup needs an additional bit to be
set. Add PTE initialization flags to handle setup default PTE
on a per-ASIC basis.
While at it, fixup the coding style too.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 1 |
3 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index af6052025c7a..b62fa7e92c79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -356,6 +356,7 @@ struct amdgpu_gmc { u64 MC_VM_MX_L1_TLB_CNTL; u64 noretry_flags; + u64 init_pte_flags; bool flush_tlb_needs_extra_type_0; bool flush_tlb_needs_extra_type_2; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index c7a7d51080a8..31a437ce9570 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -367,6 +367,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo *ancestor = &vmbo->bo; unsigned int entries; struct amdgpu_bo *bo = &vmbo->bo; + uint64_t value = 0, flags = 0; uint64_t addr; int r, idx; @@ -404,7 +405,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, addr = 0; - uint64_t value = 0, flags = 0; if (adev->asic_type >= CHIP_VEGA10) { if (level != AMDGPU_VM_PTB) { /* Handle leaf PDEs as PTEs */ @@ -413,7 +413,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, &value, &flags); } else { /* Workaround for fault priority problem on GMC9 */ - flags = AMDGPU_PTE_EXECUTABLE; + flags = AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 8037217c5fe8..dfb06baea1ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -656,6 +656,7 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 1, 0): gmc_v12_1_set_gmc_funcs(adev); + adev->gmc.init_pte_flags = AMDGPU_PTE_IS_PTE; break; default: gmc_v12_0_set_gmc_funcs(adev); |