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| author | Dave Airlie <airlied@redhat.com> | 2024-08-16 12:56:37 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2024-08-16 12:56:42 +1000 |
| commit | a809b92ee0f84c3f655b16a8b4d04bc3665d954a (patch) | |
| tree | 58f6586edc13a918d377bb16d8fef25fc9e7165a /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | 4e996697a443a214887ef81b008c344d183b5659 (diff) | |
| parent | db639278e6217173c21bf8bd52eff2e9a0d6919e (diff) | |
Merge tag 'drm-intel-next-2024-08-13' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
- Type-C programming fix for MTL+ (Gustavo)
- Fix display clock workaround (Mitul)
- Fix DP LTTPR detection (Imre)
- Calculate vblank delay more accurately (Ville)
- Make vrr_{enabling,disabling}() usable outside intel_display.c (Ville)
- FBC clean-up (Ville)
- DP link-training fixes and clean-up (Imre)
- Make I2C terminology more inclusive (Easwar)
- Make read-only array bw_gbps static const (Colin)
- HDCP fixes and improvements (Suraj)
- DP VSC SDP fixes and clean-ups (Suraj, Mitul)
- Fix opregion leak in Xe code (Lucas)
- Fix possible int overflow in skl_ddi_calculate_wrpll (Nikita)]
- General display clean-ups and conversion towards intel_display (Jani)
- On DP MST, Enable LT fallback for UHBR<->non-UHBR rates (Imre)
- Add VRR condition for DPKGC Enablement (Suraj)
- Use backlight power constants (Zimmermann)
- Correct dual pps handling for MTL_PCH+ (Dnyaneshwar)
- Dump DSC HW state (Imre)
- Replace double blank with single blank after comma (Andi)
- Read display register timeout on BMG (Mitul)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZruWsyTv3nzdArDk@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 16d5550f7e5e..aa3ba66c5307 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -23,7 +23,10 @@ #include <linux/time.h> +#include <drm/drm_fixed.h> + #include "soc/intel_dram.h" + #include "hsw_ips.h" #include "i915_reg.h" #include "intel_atomic.h" @@ -2750,7 +2753,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) */ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; int min_cdclk_bj = - (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * + (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * pixel_clock) / (2 * bigjoiner_interface_bits); min_cdclk = max(min_cdclk, min_cdclk_bj); |