diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2025-07-22 15:56:18 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-07-23 09:13:27 +0300 |
| commit | 8921dce70d46e3156b5a0b21675f5ac90903d81d (patch) | |
| tree | 45e3eca6d5aa41561f85267a44e17958797c46a8 /drivers/gpu/drm/i915/display/intel_cx0_phy.c | |
| parent | cf433f94f188782166598300c4c05274fd13c5a7 (diff) | |
drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read
According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.
v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes
Bspec: 68962
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cx0_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index a203937d66db..801235a5bc0a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3251,6 +3251,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, wakeref = intel_cx0_phy_transaction_begin(encoder); + if (intel_encoder_is_c10phy(encoder)) + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); + for (i = 0; i < 4; i++) { int tx = i % 2 + 1; u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; |