diff options
| author | Imre Deak <imre.deak@intel.com> | 2023-09-21 22:51:52 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2023-09-28 12:52:07 +0300 |
| commit | 78015e27b7d75ec497a9b5f14a7dc0ee9288d560 (patch) | |
| tree | 1470398d920c1b7107178c7c074bdabcbcd72836 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 7d0f2f68b661e5fb4bc833d6ca22974134220e99 (diff) | |
drm/i915/dp: Update the link bpp limits for DSC mode
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and starts to check the link bpp limits in DSC mode as well.
While at it add more detail to the link limit debug print and print it
also for DSC mode.
v2:
- Add to_bpp_frac_dec() instead of open coding it. (Jani)
v3: (Ville)
- Add BPP_X16_FMT / BPP_X16_ARG.
- Add TODO: comment about initializing the DSC link bpp limits earlier.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-5-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 076c4346dd2d..c1e8aa5e2f53 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -295,9 +295,10 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder, return 0; } -static void +static bool intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, + bool dsc, struct link_config_limits *limits) { /* @@ -323,8 +324,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp); - limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp); + return intel_dp_compute_config_link_bpp_limits(intel_dp, + crtc_state, + dsc, + limits); } static int intel_dp_mst_compute_config(struct intel_encoder *encoder, @@ -347,9 +350,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->has_pch_encoder = false; - intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits); - - dsc_needed = intel_dp->force_dsc_en; + dsc_needed = intel_dp->force_dsc_en || + !intel_dp_mst_compute_config_limits(intel_dp, + pipe_config, + false, + &limits); if (!dsc_needed) { ret = intel_dp_mst_compute_link_config(encoder, pipe_config, @@ -368,6 +373,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(intel_dp->force_dsc_en)); + if (!intel_dp_mst_compute_config_limits(intel_dp, + pipe_config, + true, + &limits)) + return -EINVAL; + /* * FIXME: As bpc is hardcoded to 8, as mentioned above, * WARN and ignore the debug flag force_dsc_bpc for now. |