Merge tag 'drm-intel-next-2023-11-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

drm/i915 feature pull for v6.8:

Features and functionality:
- Major DP MST improvements on bandwidth management, DSC (Imre, Stan, Ville)
- DP panel replay enabling (Animesh, Jouni)
- MTL C20 phy state verification (Mika)
- MTL DP DSC fractional bpp support (Ankit, Vandita, Swati, Imre)
- Audio fastset support (Ville)

Refactoring and cleanups:
- Use dma fence interfaces instead of i915_sw_fence (Jouni)
- Separate gem and display code (Jouni, Juha-Pekka)
- AUX register macro refactoring (Jani)
- Separate display module/device parameters from the rest (Jouni)
- Move display capabilities debugfs under display (Vinod)
- Makefile cleanup (Jani)
- Register cleanups (Ville)
- Enginer iterator cleanups (Tvrtko)
- Move display lock inits under display/ (Jani)
- VLV/CHV DPIO PHY register and interface refactoring (Jani)
- DSI VBT sequence refactoring (Jani, Andy Shevchenko)
- C10/C20 PHY PLL hardware readout and calculation abstractions (Lucas)
- DPLL code cleanups (Ville)
- Cleanup PXP plane protection checks (Jani)

Fixes:
- Replace VLV/CHV DSI GPIO direct access with proper GPIO API usage (Andy Shevchenko)
- Fix VLV/CHV DSI GPIO wrong initial value (Hans de Goede)
- Fix UHBR data, link M/N/TU and PBN values (Imre)
- Fix HDCP state on an enable/disable cycle (Suraj)
- Fix DP MST modeset sequence to be according to spec (Ville)
- Improved atomicity for multi-pipe commits (Ville)
- Update URLs in i915 MAINTAINERS entry and code (Jani)
- Check for VGA converter presence in eDP probe (Ville)
- Fix surface size checks (Ville)
- Fix LNL port/phy assignment (Lucas)
- Reset C10/C20 message bus harder to avoid sporadic failures (Mika)
- Fix bogus VBT HDMI level shift on BDW (Ville)
- Add workaround for LNL underruns when enabling FBC (Vinod)
- DSB refactoring (Animesh)
- DPT refactoring (Juha-Pekka)
- Disable DSC on DP MST on ICL (Imre)
- Fix PSR VSC packet setup timing (Mika)
- Fix LUT rounding and conversions (Ville)

DRM core display changes:
- DP MST fixes, helpers, refactoring to support bandwidth management (Imre)
- DP MST PBN divider value refactoring and fixes (Imre)
- DPCD register definitions (Ankit, Imre)
- Add helper to get DSC bpp precision (Ankit)
- Fix color LUT rounding (Ville)

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v89sl2ao.fsf@intel.com
[sima: Some conflicts in the amdgpu dp mst code]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 82 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/display/intel_dsb_buffer.c b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
new file mode 100644
index 000000000000..c77d48bda26a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023, Intel Corporation.
+ */
+
+#include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+#include "i915_vma.h"
+#include "intel_display_types.h"
+#include "intel_dsb_buffer.h"
+
+u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
+{
+	return i915_ggtt_offset(dsb_buf->vma);
+}
+
+void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
+{
+	dsb_buf->cmd_buf[idx] = val;
+}
+
+u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
+{
+	return dsb_buf->cmd_buf[idx];
+}
+
+void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
+{
+	WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
+
+	memset(&dsb_buf->cmd_buf[idx], val, size);
+}
+
+bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	u32 *buf;
+
+	if (HAS_LMEM(i915)) {
+		obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size),
+						  I915_BO_ALLOC_CONTIGUOUS);
+		if (IS_ERR(obj))
+			return false;
+	} else {
+		obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size));
+		if (IS_ERR(obj))
+			return false;
+
+		i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+	}
+
+	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
+	if (IS_ERR(vma)) {
+		i915_gem_object_put(obj);
+		return false;
+	}
+
+	buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
+	if (IS_ERR(buf)) {
+		i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP);
+		return false;
+	}
+
+	dsb_buf->vma = vma;
+	dsb_buf->cmd_buf = buf;
+	dsb_buf->buf_size = size;
+
+	return true;
+}
+
+void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
+{
+	i915_vma_unpin_and_release(&dsb_buf->vma, I915_VMA_RELEASE_MAP);
+}
+
+void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
+{
+	i915_gem_object_flush_map(dsb_buf->vma->obj);
+}