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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2024-08-22 11:44:48 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2024-09-11 21:00:49 +0530 |
| commit | 26c85e7f40f9aed4f5f04dcb0ea0bce5d44f6f54 (patch) | |
| tree | 65cf5c30bf98b7bdcc6737272510476a21ec7165 /drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | |
| parent | 9c2338ac4543e0fab3a1e0f9f025591e0f0d9f8f (diff) | |
drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates
In case of UHBR rates, we do not need to explicitly enable FEC by writing
to DP_TP_CTL register.
For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
setting fec_enable to false. However, it gets overwritten in
intel_dp_dsc_compute_config(). This change keeps fec_enable false across
MST and SST use-cases for UHBR rates.
While at it, add a comment explaining why we don't enable FEC in eDP v1.5.
v2: Correct logic to cater to SST use-cases (Jani)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822061448.4085693-1-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_hdcp_gsc.h')
0 files changed, 0 insertions, 0 deletions