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authorDave Airlie <airlied@redhat.com>2020-12-10 16:55:41 +1000
committerDave Airlie <airlied@redhat.com>2020-12-10 16:55:53 +1000
commitb10733527bfd864605c33ab2e9a886eec317ec39 (patch)
treed7d671d2fa69e628e2ac898ba8e9ab10c6481c3c /drivers/gpu/drm/radeon/evergreen_cs.c
parent60f2f74978e69fdb63e7a26179cbd5c50d4845c2 (diff)
parentf8aab60422c371425365d386dfd51e0c6c5b1041 (diff)
Merge tag 'amd-drm-next-5.11-2020-12-09' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.11-2020-12-09: amdgpu: - SR-IOV fixes - Navy Flounder updates - Sienna Cichlid updates - Dimgrey Cavefish updates - Vangogh updates - Misc SMU fixes - Misc display fixes - Last big hunk of W=1 warning fixes - Cursor validation fixes - CI BACO updates From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201210045344.21566-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index c410cad28f19..0de79f3a7e3f 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -28,6 +28,7 @@
#include "radeon.h"
#include "radeon_asic.h"
+#include "r600.h"
#include "evergreend.h"
#include "evergreen_reg_safe.h"
#include "cayman_reg_safe.h"
@@ -37,8 +38,6 @@
#define REG_SAFE_BM_SIZE ARRAY_SIZE(evergreen_reg_safe_bm)
-int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
- struct radeon_bo_list **cs_reloc);
struct evergreen_cs_track {
u32 group_size;
u32 nbanks;
@@ -1015,7 +1014,7 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
/**
* evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
- * @parser: parser structure holding parsing context.
+ * @p: parser structure holding parsing context.
*
* This is an Evergreen(+)-specific function for parsing VLINE packets.
* Real work is done by r600_cs_common_vline_parse function.
@@ -1087,7 +1086,7 @@ static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
/**
* evergreen_cs_handle_reg() - process registers that need special handling.
- * @parser: parser structure holding parsing context
+ * @p: parser structure holding parsing context
* @reg: register we are testing
* @idx: index into the cs buffer
*/
@@ -1747,7 +1746,7 @@ static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
/**
* evergreen_is_safe_reg() - check if register is authorized or not
- * @parser: parser structure holding parsing context
+ * @p: parser structure holding parsing context
* @reg: register we are testing
*
* This function will test against reg_safe_bm and return true