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authorLinus Torvalds <torvalds@linux-foundation.org>2011-02-15 15:25:33 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2011-02-15 15:25:33 -0800
commitb90be8662b1d7bd84637edb8f96e904f865a2fe2 (patch)
tree814e9fcace371347ded09bce56726ef31a55da25 /drivers/gpu/drm/radeon/r600_blit.c
parentc612cc211d7f3ba4c4626d55166b3103d15efd76 (diff)
parent5b40ddf888398ce4cccbf3b9d0a18d90149ed7ff (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (27 commits) drm/radeon/kms: hopefully fix pll issues for real (v3) drm/radeon/kms: add bounds checking to avivo pll algo drm: fix wrong usages of drm_device in DRM Developer's Guide drm/radeon/kms: fix a few more atombios endian issues drm/radeon/kms: improve 6xx/7xx CS error output drm/radeon/kms: check AA resolve registers on r300 drm/radeon/kms: fix tracking of BLENDCNTL, COLOR_CHANNEL_MASK, and GB_Z on r300 drm/radeon/kms: use linear aligned for evergreen/ni bo blits drm/radeon/kms: use linear aligned for 6xx/7xx bo blits drm/radeon: fix race between GPU reset and TTM delayed delete thread. drm/radeon/kms: evergreen/ni big endian fixes (v2) drm/radeon/kms: 6xx/7xx big endian fixes drm/radeon/kms: atombios big endian fixes drm/radeon: 6xx/7xx non-kms endian fixes drm/radeon/kms: optimize CS state checking for r100->r500 drm: do not leak kernel addresses via /proc/dri/*/vma drm/radeon/kms: add connector table for mac g5 9600 radeon mkregtable: Add missing fclose() calls drm/radeon/kms: fix interlaced modes on dce4+ drm/radeon: fix memory debugging since d961db75ce86a84f1f04e91ad1014653ed7d9f46 ...
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index ca5c29f70779..7f1043448d25 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -137,9 +137,9 @@ set_shaders(struct drm_device *dev)
ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
for (i = 0; i < r6xx_vs_size; i++)
- vs[i] = r6xx_vs[i];
+ vs[i] = cpu_to_le32(r6xx_vs[i]);
for (i = 0; i < r6xx_ps_size; i++)
- ps[i] = r6xx_ps[i];
+ ps[i] = cpu_to_le32(r6xx_ps[i]);
dev_priv->blit_vb->used = 512;
@@ -192,6 +192,9 @@ set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
DRM_DEBUG("\n");
sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
+#ifdef __BIG_ENDIAN
+ sq_vtx_constant_word2 |= (2 << 30);
+#endif
BEGIN_RING(9);
OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
@@ -291,7 +294,11 @@ draw_auto(drm_radeon_private_t *dev_priv)
OUT_RING(DI_PT_RECTLIST);
OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+#ifdef __BIG_ENDIAN
+ OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
+#else
OUT_RING(DI_INDEX_SIZE_16_BIT);
+#endif
OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
OUT_RING(1);