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authorGabe Teeger <gabe.teeger@amd.com>2026-09-03 11:58:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-09-17 11:38:26 -0400
commit3366975818ebff2890d6f712c76acea3d0a81f3b (patch)
tree2099c00856511da139e5ced5cc74d1dc9152b67e /drivers/gpu/drm
parent60484b2f024b6a992da050fad1ee39af304fd4d2 (diff)
drm/amd/display: Remove MALL capabilities from DCN42B bounding box
[Why] DCN42B has no MALL, but MALL capabilities are non-zero. [How] Zero out MALL capabilities in the dcn42b bounding box. Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
index 0f8666788bbb..e83a9ac018db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
@@ -202,7 +202,7 @@ static const struct dml2_soc_bb dml2_socbb_dcn42b = {
.xtalclk_mhz = 24,
.pcie_refclk_mhz = 100,
.dchub_refclk_mhz = 50,
- .mall_allocated_for_dcn_mbytes = 64,
+ .mall_allocated_for_dcn_mbytes = 0,
.max_outstanding_reqs = 256,
.fabric_datapath_to_dcn_data_return_bytes = 32,
.return_bus_width_bytes = 64,