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authorZhigang Luo <Zhigang.Luo@amd.com>2026-08-31 15:39:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-10-07 12:02:46 -0400
commit010e510347f522f5c83c5bd1124b5de9c7f52c27 (patch)
tree74536c7d1e0b4e3bbd376f3c66f031b99cd5850b /drivers/gpu
parent489ee1c344db5fa43d643da05af77e9061195e56 (diff)
drm/amdgpu: mark A+A VF VRAM mappings as system memory
On the A+A VF the GPU reaches its HBM over the system memory path at a system physical address, so page table entries covering VRAM have to carry AMDGPU_PTE_SYSTEM and the addresses they hold have to be physical rather than MC addresses. Set the SYSTEM bit in the PDB0 entries and in amdgpu_ttm_tt_pde_flags(), and convert the VRAM address in amdgpu_gmc_get_pde_for_bo() with amdgpu_gmc_vram_mc2pa(). NPA mappings still require VSCT=0011 (PTE.S=0). Clear SYSTEM in gmc_v12_1_get_npa_flags() and amdgpu_ualink_peer_remote_init() so NPA PTEs do not inherit the VRAM SYSTEM bit. v2: - Use (sriov_vf || passthrough) and amdgpu_virt_vram_is_spm() for PDB0/TTM SYSTEM bits and mc2pa. v3: - Rely on amdgpu_virt_vram_is_spm() without redundant VF/passthrough checks. v4: - Explicitly clear AMDGPU_PTE_SYSTEM for NPA (VSCT=0011). Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c1
4 files changed, 22 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 167f1344f8f4..d25ca903e21b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -122,6 +122,11 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
break;
case TTM_PL_VRAM:
*addr = amdgpu_bo_gpu_offset(bo);
+ /* For SPM-backed VRAM, convert the MC address to a physical
+ * address for system memory path access.
+ */
+ if (amdgpu_virt_vram_is_spm(adev))
+ *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
break;
default:
*addr = 0;
@@ -1260,6 +1265,8 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
flags |= AMDGPU_PTE_WRITEABLE;
flags |= AMDGPU_PTE_SNOOPED;
+ if (amdgpu_virt_vram_is_spm(adev))
+ flags |= AMDGPU_PTE_SYSTEM;
flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
flags |= AMDGPU_PDE_PTE_FLAG(adev);
@@ -1279,6 +1286,8 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
* pointing to a 4K system page
*/
flags = AMDGPU_PTE_VALID;
+ if (amdgpu_virt_vram_is_spm(adev))
+ flags |= AMDGPU_PTE_SYSTEM;
flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0);
/* Requires gart_ptb_gpu_pa to be 4K aligned */
amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index a3777ceb638f..6b3fbf79abc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1460,9 +1460,17 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
flags |= AMDGPU_PTE_SNOOPED;
}
- if (mem && mem->mem_type == TTM_PL_VRAM &&
- mem->bus.caching == ttm_cached)
- flags |= AMDGPU_PTE_SNOOPED;
+ if (mem && mem->mem_type == TTM_PL_VRAM) {
+ if (mem->bo) {
+ struct amdgpu_device *adev = amdgpu_ttm_adev(mem->bo->bdev);
+
+ if (amdgpu_virt_vram_is_spm(adev))
+ flags |= AMDGPU_PTE_SYSTEM;
+ }
+
+ if (mem->bus.caching == ttm_cached)
+ flags |= AMDGPU_PTE_SNOOPED;
+ }
return flags;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
index 8fed28dc7502..6b1d9f671905 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
@@ -6141,6 +6141,7 @@ static int amdgpu_ualink_peer_remote_init(struct amdgpu_device *adev)
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, bo->tbo.resource);
flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT_GFX12 | AMDGPU_PTE_BUS_ATOMICS;
flags &= ~AMDGPU_PTE_VALID;
+ flags &= ~AMDGPU_PTE_SYSTEM;
/* PTE.X=0 turn off RPC checks for RBs, wptr and doorbell NPA address */
flags &= ~AMDGPU_PTE_EXECUTABLE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
index 57aac3a9a3b0..df72eb2b67ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
@@ -616,6 +616,7 @@ static void gmc_v12_1_get_npa_flags(struct amdgpu_device *adev,
*flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT_GFX12 |
AMDGPU_PTE_BUS_ATOMICS;
*flags &= ~AMDGPU_PTE_VALID;
+ *flags &= ~AMDGPU_PTE_SYSTEM;
*flags &= ~AMDGPU_PTE_EXECUTABLE;
}