drm/amd/display: Cap DSC bpp for USB4 DP tunnels

On pre-DCN4.2 platforms, USB4 DP bandwidth allocation is unavailable.
SST and MST streams are sized against their native DP link bandwidth
even when multiple DP tunnels share the host router. A high-bandwidth
DSC stream can consume too much shared tunnel capacity and cause
intermittent display corruption when another tunnel is active.

Cap the DSC target at 8 bpp for USB4 DPIA SST and MST streams when
bandwidth allocation is unavailable. For MST, cap the DSC fairness
range while preserving its per-link allocation. When bandwidth
allocation is enabled on DCN4.2, retain forced DSC and the existing
minimum-bpp behavior required to fit the tunnel grant.

This is a follow-up to commit c30b9813bce1 ("drm/amd/display: Force DSC
to 8bpp for SST DP tunneling over USB4") and commit cd53dcd2a7d7
("drm/amd/display: Force DSC to 8bpp for MST DP tunneling over USB4").

Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e2bd5d908a89252ad4ee11a3dbc9fd57c257accd)

2 files changed, 15 insertions, 8 deletions

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index 2b81396bd06e..ef28d2143b52 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -1289,10 +1289,10 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
 	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
 							dc_link_get_link_cap(aconnector->dc_link));
 
-	if (aconnector->dc_link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
-	    aconnector->dc_link->dpia_bw_alloc_config.bw_alloc_enabled) {
+	if (aconnector->dc_link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 		dsc_options.max_target_bpp_limit_override_x16 = 8 * 16;
-		dsc_options.force_dsc_when_not_needed = true;
+		if (aconnector->dc_link->dpia_bw_alloc_config.bw_alloc_enabled)
+			dsc_options.force_dsc_when_not_needed = true;
 	}
 
 	/* Set DSC policy according to dsc_clock_en */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ee3f3df6bb8d..5697645ef7cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1342,6 +1342,8 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
 	DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);
 	for (i = 0; i < dc_state->stream_count; i++) {
 		struct dc_dsc_policy dsc_policy = {0};
+			u32 min_target_bpp_x16;
+			u32 max_target_bpp_x16;
 
 		stream = dc_state->streams[i];
 
@@ -1380,7 +1382,15 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
 		    dc_link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 		    dc_link->dpia_bw_alloc_config.bw_alloc_enabled)
 			params[count].clock_force_enable = DSC_CLK_FORCE_ENABLE;
+
 		dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
+		min_target_bpp_x16 = dsc_policy.min_target_bpp * 16;
+		max_target_bpp_x16 = dsc_policy.max_target_bpp * 16;
+		if (dc_link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
+			max_target_bpp_x16 = min_t(u32, max_target_bpp_x16, 8 * 16);
+			if (dc_link->dpia_bw_alloc_config.bw_alloc_enabled)
+				max_target_bpp_x16 = min_target_bpp_x16;
+		}
 		is_frl_endpoint_present = get_conv_frl_bw(aconnector, &frl_conv_bw_in_kbps, &frl_conv_dsc_bw_in_kbps);
 		if (stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported &&
 				is_frl_endpoint_present &&
@@ -1390,11 +1400,8 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
 		if (!dc_dsc_compute_bandwidth_range(
 				stream->sink->ctx->dc->res_pool->dscs[0],
 				stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
-				dsc_policy.min_target_bpp * 16,
-				(dc_link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
-				 dc_link->dpia_bw_alloc_config.bw_alloc_enabled) ?
-					dsc_policy.min_target_bpp * 16 :
-					dsc_policy.max_target_bpp * 16,
+				min_target_bpp_x16,
+				max_target_bpp_x16,
 				&stream->sink->dsc_caps.dsc_dec_caps,
 				&stream->timing,
 				dc_link_get_highest_encoding_format(dc_link),