diff options
| author | Imre Deak <imre.deak@intel.com> | 2025-12-22 17:35:31 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2026-01-13 18:42:13 +0200 |
| commit | 44a95ffe685d3b9428ab81f632e9b34bb2e4641c (patch) | |
| tree | 3069fa702fd6eb37b1a83f99857c1b339a21d0e5 /drivers/gpu | |
| parent | 85b4360d2b72b4a38497f5267da5cb817dd91b34 (diff) | |
drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16()
Factor out align_max_vesa_compressed_bpp_x16(), also used later for
computing the maximum DSC compressed BPP limit.
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251222153547.713360-5-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp.c | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5b08d308ead1..9d7a1df179a4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -868,10 +868,23 @@ small_joiner_ram_size_bits(struct intel_display *display) return 6144 * 8; } +static int align_max_vesa_compressed_bpp_x16(int max_link_bpp_x16) +{ + int i; + + for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) { + int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]); + + if (vesa_bpp_x16 <= max_link_bpp_x16) + return vesa_bpp_x16; + } + + return 0; +} + static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) { u32 bits_per_pixel = bpp; - int i; /* Error out if the max bpp is less than smallest allowed valid bpp */ if (bits_per_pixel < valid_dsc_bpp[0]) { @@ -900,15 +913,13 @@ static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp } bits_per_pixel = min_t(u32, bits_per_pixel, 27); } else { + int link_bpp_x16 = fxp_q4_from_int(bits_per_pixel); + /* Find the nearest match in the array of known BPPs from VESA */ - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { - if (bits_per_pixel < valid_dsc_bpp[i + 1]) - break; - } - drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", - bits_per_pixel, valid_dsc_bpp[i]); + link_bpp_x16 = align_max_vesa_compressed_bpp_x16(link_bpp_x16); - bits_per_pixel = valid_dsc_bpp[i]; + drm_WARN_ON(display->drm, fxp_q4_to_frac(link_bpp_x16)); + bits_per_pixel = fxp_q4_to_int(link_bpp_x16); } return bits_per_pixel; @@ -2220,7 +2231,6 @@ int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) { struct intel_display *display = to_intel_display(intel_dp); - int i; if (DISPLAY_VER(display) >= 13) { if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) @@ -2232,12 +2242,7 @@ bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) if (fxp_q4_to_frac(bpp_x16)) return false; - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { - if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) - return true; - } - - return false; + return align_max_vesa_compressed_bpp_x16(bpp_x16) == bpp_x16; } /* |