diff options
| author | Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2021-04-22 19:05:44 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-04-26 17:01:34 -0700 |
| commit | 8804325861be242a420d68c0175127a5947ac35a (patch) | |
| tree | 2f931ac8ad18d10b0be86aa0bd6c3888d60337e7 /drivers/gpu | |
| parent | d5b5f63cc5b0e7cf9b16b694215bc43fb6b71441 (diff) | |
drm/i915/display: Disable PSR2 if TGL Display stepping is B1 from A0
TGL PSR2 hardware tracking shows momentary flicker and screen shift if
TGL Display stepping is B1 from A0.
It has been fixed from TGL Display stepping C0.
HSDES: 18015970021
HSDES: 2209313811
BSpec: 55378
v2: Add checking of PSR2 manual tracking (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210422160544.2427123-1-gwan-gyeong.mun@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 66335ec6b7d1..c61e1d774667 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -817,6 +817,13 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, } } + /* Wa_2209313811 */ + if (!crtc_state->enable_psr2_sel_fetch && + IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); + return false; + } + if (!crtc_state->enable_psr2_sel_fetch && (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { drm_dbg_kms(&dev_priv->drm, |