diff options
| author | Zhigang Luo <Zhigang.Luo@amd.com> | 2026-08-31 14:35:31 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-10-07 12:02:18 -0400 |
| commit | 9a403dc60f4c54cb81eb60fa8d639c59805fb38f (patch) | |
| tree | 2c677fcd674f0268c54d1164f9fc407597b250d8 /drivers/gpu | |
| parent | 2ff39b798b8c300ddaabb9d957b5852b2a3c940b (diff) | |
drm/amdgpu: add helper for VRAM in system physical memory
On A+A, HBM is reached at a host physical address, so VRAM mappings
need the system-memory path. That is true for both an SR-IOV VF and a
passthrough VM; native PF A+A keeps the mmhub/sysvm path.
Add AMDGPU_VIRT_VRAM_IS_SPM and amdgpu_virt_vram_is_spm() so later
patches can identify SPM-backed VRAM without repeating the cap test.
v2:
- Rename the helper to amdgpu_virt_vram_is_spm(); it only tests
AMDGPU_VIRT_VRAM_IS_SPM.
- Set the cap in ip_early_init when an SR-IOV VF or passthrough dGPU
has no FB BAR0, after AMD_IS_APU is known.
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com>
Signed-off-by: Fangsheng Huang <Fangsheng.Huang@amd.com>
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 |
2 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2af5c282eae4..e7b0b2e1cd73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2078,10 +2078,15 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) !dev_is_removable(&adev->pdev->dev)) adev->flags |= AMD_IS_PX; - if (!(adev->flags & AMD_IS_APU)) + if (!(adev->flags & AMD_IS_APU)) { adev->has_pr3 = adev->link_partner && pci_pr3_present(adev->link_partner); + if ((amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) && + !pci_resource_len(adev->pdev, 0)) + adev->virt.caps |= AMDGPU_VIRT_VRAM_IS_SPM; + } + adev->pm.pp_feature = amdgpu_pp_feature_mask; if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) adev->pm.pp_feature &= ~PP_GFXOFF_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 9957241bdf59..a2c1aa838737 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -32,6 +32,7 @@ #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ +#define AMDGPU_VIRT_VRAM_IS_SPM (1 << 6) /* FB BAR0 is absent; VRAM is SPM */ /* flags for indirect register access path supported by rlcg for sriov */ #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) @@ -406,6 +407,9 @@ struct amdgpu_video_codec_info; #define amdgpu_passthrough(adev) \ ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) +#define amdgpu_virt_vram_is_spm(adev) \ +((adev)->virt.caps & AMDGPU_VIRT_VRAM_IS_SPM) + #define amdgpu_sriov_vf_mmio_access_protection(adev) \ ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) |