diff options
| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2025-08-19 16:55:32 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-01-05 16:27:31 -0500 |
| commit | bc35ae1a09ca02c25df54327fb1e7a09d2556e1a (patch) | |
| tree | 81a188ff45d3d5dfb92270f677cbace177eee4e2 /drivers/gpu | |
| parent | 09a75a234b21e6564e2c0bac517cf5bd2c6e1905 (diff) | |
drm/amdgpu: Fix xcc_id input for soc_v1_0_grbm_select
Ensure the GRBM_GFX_CNTL is programmed correctly
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 321ca7ac2693..64b949195587 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -1448,7 +1448,7 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); } } - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); mutex_unlock(&adev->srbm_mutex); @@ -1776,7 +1776,7 @@ static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, mec_hdr->ucode_start_addr_hi >> 2); } - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); /* reset mec pipe */ tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); @@ -1821,7 +1821,7 @@ static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, cp_hdr->ucode_start_addr_hi >> 2); } - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); mutex_unlock(&adev->srbm_mutex); } @@ -2017,7 +2017,7 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); } mutex_unlock(&adev->srbm_mutex); - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); /* Trigger an invalidation of the L1 instruction caches */ tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); |