summaryrefslogtreecommitdiff
path: root/drivers/mailbox
diff options
context:
space:
mode:
authorJjian Zhou <jjian.zhou@mediatek.com>2025-10-13 14:31:36 +0800
committerJassi Brar <jassisinghbrar@gmail.com>2026-01-18 12:50:45 -0600
commitb562abd956726f57bb78813b4c77db51d28933a9 (patch)
tree56f8ae94de01929e841b89beea3da73f31acfa70 /drivers/mailbox
parentc2b75a5353aec990bbb8bd53737d39b497a7bdaa (diff)
mailbox: mediatek: Add mtk-vcp-mailbox driver
Add mtk-vcp-mailbox driver to support the communication with VCP remote microprocessor. Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Diffstat (limited to 'drivers/mailbox')
-rw-r--r--drivers/mailbox/Kconfig9
-rw-r--r--drivers/mailbox/Makefile2
-rw-r--r--drivers/mailbox/mtk-vcp-mailbox.c170
3 files changed, 181 insertions, 0 deletions
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 29f16f220384..d7f8db25f3b3 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -304,6 +304,15 @@ config MTK_GPUEB_MBOX
Say Y or m here if you want to support the MT8196 SoC in your kernel
build.
+config MTK_VCP_MBOX
+ tristate "MediaTek VCP Mailbox Support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ help
+ Say yes here to add support for the MediaTek VCP mailbox driver.
+ The mailbox implementation provides access from the application
+ processor to Video Companion Processor Unit.
+ If unsure say N.
+
config ZYNQMP_IPI_MBOX
tristate "Xilinx ZynqMP IPI Mailbox"
depends on ARCH_ZYNQMP && OF
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 81820a4f5528..944d8ea39f34 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -65,6 +65,8 @@ obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o
obj-$(CONFIG_MTK_GPUEB_MBOX) += mtk-gpueb-mailbox.o
+obj-$(CONFIG_MTK_VCP_MBOX) += mtk-vcp-mailbox.o
+
obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o
diff --git a/drivers/mailbox/mtk-vcp-mailbox.c b/drivers/mailbox/mtk-vcp-mailbox.c
new file mode 100644
index 000000000000..cedad575528f
--- /dev/null
+++ b/drivers/mailbox/mtk-vcp-mailbox.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Corporation. All rights reserved.
+ * Author: Jjian Zhou <jjian.zhou.@mediatek.com>
+ */
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-vcp-mailbox.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+struct mtk_vcp_mbox {
+ struct mbox_controller mbox;
+ void __iomem *base;
+ struct device *dev;
+ const struct mtk_vcp_mbox_cfg *cfg;
+ struct mtk_ipi_info ipi_recv;
+ struct mbox_chan chans;
+};
+
+struct mtk_vcp_mbox_cfg {
+ u16 set_in;
+ u16 clr_out;
+};
+
+static irqreturn_t mtk_vcp_mbox_irq_thread(int irq, void *data)
+{
+ struct mtk_vcp_mbox *priv = data;
+
+ /* get irq status */
+ priv->ipi_recv.irq_status = readl(priv->base + priv->cfg->clr_out);
+
+ __ioread32_copy(priv->ipi_recv.msg, priv->base,
+ MTK_VCP_MBOX_SLOT_MAX_SIZE / 4);
+
+ mbox_chan_received_data(&priv->chans, &priv->ipi_recv);
+
+ /* clear irq status */
+ writel(priv->ipi_recv.irq_status, priv->base + priv->cfg->clr_out);
+
+ return IRQ_HANDLED;
+}
+
+static struct mbox_chan *mtk_vcp_mbox_xlate(struct mbox_controller *mbox,
+ const struct of_phandle_args *sp)
+{
+ if (sp->args_count)
+ return NULL;
+
+ return &mbox->chans[0];
+}
+
+static int mtk_vcp_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ struct mtk_vcp_mbox *priv = chan->con_priv;
+ struct mtk_ipi_info *ipi_info = data;
+ u32 status;
+
+ if (!ipi_info->msg) {
+ dev_err(priv->dev, "msg buffer is NULL.\n");
+ return -EINVAL;
+ }
+
+ status = readl(priv->base + priv->cfg->set_in);
+ if (status & BIT(ipi_info->index)) {
+ dev_warn(priv->dev, "mailbox IPI %d is busy.\n", ipi_info->id);
+ return -EBUSY;
+ }
+
+ if (ipi_info->slot_ofs + ipi_info->len > MTK_VCP_MBOX_SLOT_MAX_SIZE)
+ return -EINVAL;
+ __iowrite32_copy(priv->base + ipi_info->slot_ofs, ipi_info->msg,
+ ipi_info->len);
+
+ writel(BIT(ipi_info->index), priv->base + priv->cfg->set_in);
+
+ return 0;
+}
+
+static bool mtk_vcp_mbox_last_tx_done(struct mbox_chan *chan)
+{
+ struct mtk_ipi_info *ipi_info = chan->active_req;
+ struct mtk_vcp_mbox *priv = chan->con_priv;
+
+ return !(readl(priv->base + priv->cfg->set_in) & BIT(ipi_info->index));
+}
+
+static const struct mbox_chan_ops mtk_vcp_mbox_chan_ops = {
+ .send_data = mtk_vcp_mbox_send_data,
+ .last_tx_done = mtk_vcp_mbox_last_tx_done,
+};
+
+static int mtk_vcp_mbox_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_vcp_mbox *priv;
+ struct mbox_controller *mbox;
+ int ret, irq;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->chans.con_priv = priv;
+ mbox = &priv->mbox;
+ mbox->dev = dev;
+ mbox->ops = &mtk_vcp_mbox_chan_ops;
+ mbox->txdone_irq = false;
+ mbox->txdone_poll = true;
+ mbox->of_xlate = mtk_vcp_mbox_xlate;
+ mbox->num_chans = 1;
+ mbox->chans = &priv->chans;
+
+ priv->ipi_recv.msg = devm_kzalloc(dev, MTK_VCP_MBOX_SLOT_MAX_SIZE,
+ GFP_KERNEL);
+ if (!priv->ipi_recv.msg)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->cfg = of_device_get_match_data(dev);
+ if (!priv->cfg)
+ return -EINVAL;
+
+ platform_set_drvdata(pdev, priv);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ mtk_vcp_mbox_irq_thread, IRQF_ONESHOT,
+ dev_name(dev), priv);
+ if (ret < 0)
+ return ret;
+
+ return devm_mbox_controller_register(dev, &priv->mbox);
+}
+
+static const struct mtk_vcp_mbox_cfg mt8196_cfg = {
+ .set_in = 0x100,
+ .clr_out = 0x10c,
+};
+
+static const struct of_device_id mtk_vcp_mbox_of_match[] = {
+ { .compatible = "mediatek,mt8196-vcp-mbox", .data = &mt8196_cfg },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_vcp_mbox_of_match);
+
+static struct platform_driver mtk_vcp_mbox_driver = {
+ .probe = mtk_vcp_mbox_probe,
+ .driver = {
+ .name = "mtk_vcp_mbox",
+ .of_match_table = mtk_vcp_mbox_of_match,
+ },
+};
+module_platform_driver(mtk_vcp_mbox_driver);
+
+MODULE_AUTHOR("Jjian Zhou <jjian.zhou@mediatek.com>");
+MODULE_DESCRIPTION("MTK VCP Mailbox Controller");
+MODULE_LICENSE("GPL");