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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2026-02-25 18:37:20 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2026-02-26 08:28:15 +0100
commitd455e0f602d7e4d4ba709418009c39be48fc2149 (patch)
treee742c76bd0645373c08e08be73189a98babb6d44 /drivers/memory/Kconfig
parent0a93f2355cf4922ad2399dbef5ea1049fef116d4 (diff)
memory: bt1-l2-ctl: Remove not-going-to-be-supported code for Baikal SoC
As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260225173930.3819351-2-andriy.shevchenko@linux.intel.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'drivers/memory/Kconfig')
-rw-r--r--drivers/memory/Kconfig11
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 79df0d22e218..e5527020ff33 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -64,17 +64,6 @@ config BRCMSTB_MEMC
controller and specifically control the Self Refresh Power Down
(SRPD) inactivity timeout.
-config BT1_L2_CTL
- bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
- depends on MIPS_BAIKAL_T1 || COMPILE_TEST
- select MFD_SYSCON
- help
- Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
- resides Coherency Manager v2 with embedded 1MB L2-cache. It's
- possible to tune the L2 cache performance up by setting the data,
- tags and way-select latencies of RAM access. This driver provides a
- dt properties-based and sysfs interface for it.
-
config TI_AEMIF
tristate "Texas Instruments AEMIF driver"
depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST