diff options
| author | Ketan Patil <ketanp@nvidia.com> | 2026-02-26 16:31:10 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2026-03-07 17:59:35 +0100 |
| commit | b8a177f18df1b439aac708da2d8bd9fcd68bb1eb (patch) | |
| tree | 9aa85806f397661f11c41450ca5a303e3bfe3d9c /drivers/memory/tegra/tegra20.c | |
| parent | 2413283fac5b2975f5ead6a1dcac7d5c6f7366d8 (diff) | |
memory: tegra: Group error handling related registers
Group MC error related registers into a struct as they could have SoC
specific values. Tegra264 has different register offsets than the
existing devices and so in order to add support for Tegra264 we need to
first make this change.
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'drivers/memory/tegra/tegra20.c')
| -rw-r--r-- | drivers/memory/tegra/tegra20.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 4748113bfe9d..1b2b598ab564 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2012-2026 NVIDIA CORPORATION. All rights reserved. */ #include <linux/bitfield.h> @@ -778,4 +778,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .num_resets = ARRAY_SIZE(tegra20_mc_resets), .icc_ops = &tegra20_mc_icc_ops, .ops = &tegra20_mc_ops, + .regs = &tegra20_mc_regs, }; |