diff options
| author | Andrew Gaylard <ag@ffroot.co.za> | 2026-09-17 12:49:59 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulfh@kernel.org> | 2026-09-29 12:00:55 +0200 |
| commit | e16268a118e75cde4eda6bc5a95d8e959aec582c (patch) | |
| tree | a6bdd71fdd606f749b8b0ed2ab0cf5af6587c537 /drivers/mmc | |
| parent | ec60f36da4100c5fd6f102b5995b4df6c926fe5a (diff) | |
mmc: sunplus: initialise rd_crc_dly=1 for DDR modes
After spmmc_controller_init() resets the controller, all timing
fields are zero. The hs_en path initialises the write timing
delays (wr_cmd_dly, wr_dat_dly) but leaves the read side at zero.
In DDR52 mode, rd_crc_dly=0 causes the first write to fail with
CRC_TOKEN_CHECK_ERROR, triggering the auto-tuning retry loop and
causing a multi-second delay on the first cold-boot write.
Set rd_crc_dly=1 when enabling DDR mode to avoid this.
Tested on a LTPP3G2, booting via eMMC in DDR52 mode,
on linux-next-20260915.
Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sunplus-mmc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/sunplus-mmc.c b/drivers/mmc/host/sunplus-mmc.c index 63279760239c..e947c84eef94 100644 --- a/drivers/mmc/host/sunplus-mmc.c +++ b/drivers/mmc/host/sunplus-mmc.c @@ -294,6 +294,11 @@ static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing) value = readl(host->base + SPMMC_SD_CONFIG0_REG); value |= SPMMC_SD_DDR_MODE; writel(value, host->base + SPMMC_SD_CONFIG0_REG); + /* DDR mode needs rd_crc_dly=1 */ + value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); + value &= ~SPMMC_SD_READ_CRC_DELAY; + value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, 1); + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); } else { value = readl(host->base + SPMMC_SD_CONFIG0_REG); value &= ~SPMMC_SD_DDR_MODE; |