diff options
| author | Hans Zhang <18255117159@163.com> | 2025-08-13 22:45:29 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-08-20 15:56:19 -0500 |
| commit | 907912c1daa7d87ec179ab35f6326e98233ae03a (patch) | |
| tree | a264774aad86932fa36c5535e01a2edaa74d707b /drivers/pci/controller/cadence/pcie-cadence.h | |
| parent | 18ac51ae9df925292a4d8ca6550a199924ae9e17 (diff) | |
PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsets
The PCI capability/extended capability offsets are not guaranteed to be the
same across all SoCs integrating the Cadence PCIe IP.
Use the cdns_pcie_find_{ext}_capability() APIs to find the capabilities,
which avoids hardcoding the offsets in the driver.
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250813144529.303548-7-18255117159@163.com
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.h')
| -rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 9eebf8f02abc..88cec0dc2067 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ |