diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:16 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:16 -0500 |
| commit | f2b2fcf6d64e45f68e1730ac0a63fe896f06241e (patch) | |
| tree | 113da04868924fc2dedc2b5059d3e19f3267e8f3 /drivers/pci/controller/dwc/pcie-designware.h | |
| parent | df1d435baafa18b1b8a923dfaf663241cde54364 (diff) | |
| parent | cef730075cfe2b2091e3c94471cc0a78405401d5 (diff) | |
Merge branch 'pci/controller/dwc'
- Add support for x16 in devicetree 'num-lanes' property (Konrad Dybcio)
* pci/controller/dwc:
PCI: dwc: Support 16-lane operation
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a44f2113925d..fa8fd9674685 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -90,6 +90,7 @@ #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) +#define PORT_LINK_MODE_16_LANES PORT_LINK_MODE(0x1f) #define PCIE_PORT_LANE_SKEW 0x714 #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) |