diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-12-17 13:15:10 +0200 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-12-30 22:41:25 +0530 |
| commit | 62d4911290f9cbb16f5b6ba6782660148a656fc7 (patch) | |
| tree | d416b487522776ba76af4965f57330642fb1b2bf /drivers/pci/controller | |
| parent | 4b86eff47e205819eb862097493ec20e25ac8f56 (diff) | |
PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS
The RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS registers are of the R/W1C
type. According to the RZ/G3S HW Manual, Rev. 1.10, chapter 34.2.1
Register Type, R/W1C register bits are cleared to 0b by writing 1b, while
writing 0b has no effect. Therefore, there is no need to take a lock
around writes to these registers.
Drop the locking.
Along with this, add a note about the R/W1C register type to the register
offset definitions.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://patch.msgid.link/20251217111510.138848-3-claudiu.beznea.uj@bp.renesas.com
Diffstat (limited to 'drivers/pci/controller')
| -rw-r--r-- | drivers/pci/controller/pcie-rzg3s-host.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index ae6d9c7dc2c1..5aa58638903f 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -73,6 +73,7 @@ #define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i) #define RZG3S_PCI_PINTRCVIE_MSI BIT(4) +/* Register is R/W1C, it doesn't require locking. */ #define RZG3S_PCI_PINTRCVIS 0x114 #define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i) #define RZG3S_PCI_PINTRCVIS_MSI BIT(4) @@ -114,6 +115,8 @@ #define RZG3S_PCI_MSIRE_ENA BIT(0) #define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10) + +/* Register is R/W1C, it doesn't require locking. */ #define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10) #define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20) @@ -507,8 +510,6 @@ static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; - guard(raw_spinlock_irqsave)(&host->hw_lock); - writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); } @@ -840,8 +841,6 @@ static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) { struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); - guard(raw_spinlock_irqsave)(&host->hw_lock); - rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); |