Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq chip driver updates from Thomas Gleixner:

 - Use the startup/shutdown callbacks for the PCI/MSI per device
   interrupt domains.

   This allows us to initialize the RISCV PLIC interrupt hierarchy
   correctly and provides a mechanism to decouple the masking and
   unmasking during run-time from the expensive PCI mask and unmask when
   the underlying MSI provider implementation allows the interrupt to be
   masked.

 - Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that
   the affinity assignment works correctly by switching it over to the
   startup/shutdown scheme

 - Allow MSI providers to opt out from masking a PCI/MSI interrupt at
   the PCI device during operation when the provider can mask the
   interrupt at the underlying interrupt chip. This reduces the overhead
   in scenarios where disable_irq()/enable_irq() is utilized frequently
   by a driver.

   The PCI/MSI device level [un]masking is only required on startup and
   shutdown in this case.

 - Remove the conditional mask/unmask logic in the PCI/MSI layer as this
   is now handled unconditionally.

 - Replace the hardcoded interrupt routing in the Loongson EIOINTC
   interrupt driver to respect the firmware settings and spread them out
   to different CPU interrupt inputs so that the demultiplexing handler
   only needs to read only a single 64-bit status register instead of
   four, which significantly reduces the overhead in VMs as the status
   register access causes a VM exit.

 - Add support for the new AST2700 SCU interrupt controllers

 - Use the legacy interrupt domain setup for the Loongson PCH-LPC
   interrupt controller, which resembles the x86 legacy PIC setup and
   has the same hardcoded legacy requirements.

 - The usual set of cleanups, fixes and improvements all over the place

* tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller
  PCI/MSI: Remove the conditional parent [un]mask logic
  irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag
  irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers
  dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles
  dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
  irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization
  irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc()
  irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path
  irqchip/gic-v5: Delete a stray tab
  irqchip/sg2042-msi: Set irq type according to DT configuration
  riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
  riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
  irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment
  irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM
  irqchip: Use int type to store negative error codes
  irqchip/gic-v5: Remove the redundant ITS cache invalidation
  PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent()
  irqchip/loongson-eiointc: Add multiple interrupt pin routing support
  irqchip/loongson-eiointc: Route interrupt parsed from bios table
  ...

1 files changed, 45 insertions, 8 deletions

diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c
index 0938ef7ebabf..dfb61f152702 100644
--- a/drivers/pci/msi/irqdomain.c
+++ b/drivers/pci/msi/irqdomain.c
@@ -148,20 +148,43 @@ static void pci_device_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *d
 	arg->hwirq = desc->msi_index;
 }
 
-static __always_inline void cond_mask_parent(struct irq_data *data)
+static void cond_shutdown_parent(struct irq_data *data)
 {
 	struct msi_domain_info *info = data->domain->host_data;
 
-	if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT))
+	if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT))
+		irq_chip_shutdown_parent(data);
+	else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT))
 		irq_chip_mask_parent(data);
 }
 
-static __always_inline void cond_unmask_parent(struct irq_data *data)
+static unsigned int cond_startup_parent(struct irq_data *data)
 {
 	struct msi_domain_info *info = data->domain->host_data;
 
-	if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT))
+	if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT))
+		return irq_chip_startup_parent(data);
+	else if (unlikely(info->flags & MSI_FLAG_PCI_MSI_MASK_PARENT))
 		irq_chip_unmask_parent(data);
+
+	return 0;
+}
+
+static void pci_irq_shutdown_msi(struct irq_data *data)
+{
+	struct msi_desc *desc = irq_data_get_msi_desc(data);
+
+	pci_msi_mask(desc, BIT(data->irq - desc->irq));
+	cond_shutdown_parent(data);
+}
+
+static unsigned int pci_irq_startup_msi(struct irq_data *data)
+{
+	struct msi_desc *desc = irq_data_get_msi_desc(data);
+	unsigned int ret = cond_startup_parent(data);
+
+	pci_msi_unmask(desc, BIT(data->irq - desc->irq));
+	return ret;
 }
 
 static void pci_irq_mask_msi(struct irq_data *data)
@@ -169,14 +192,12 @@ static void pci_irq_mask_msi(struct irq_data *data)
 	struct msi_desc *desc = irq_data_get_msi_desc(data);
 
 	pci_msi_mask(desc, BIT(data->irq - desc->irq));
-	cond_mask_parent(data);
 }
 
 static void pci_irq_unmask_msi(struct irq_data *data)
 {
 	struct msi_desc *desc = irq_data_get_msi_desc(data);
 
-	cond_unmask_parent(data);
 	pci_msi_unmask(desc, BIT(data->irq - desc->irq));
 }
 
@@ -194,6 +215,8 @@ static void pci_irq_unmask_msi(struct irq_data *data)
 static const struct msi_domain_template pci_msi_template = {
 	.chip = {
 		.name			= "PCI-MSI",
+		.irq_startup		= pci_irq_startup_msi,
+		.irq_shutdown		= pci_irq_shutdown_msi,
 		.irq_mask		= pci_irq_mask_msi,
 		.irq_unmask		= pci_irq_unmask_msi,
 		.irq_write_msi_msg	= pci_msi_domain_write_msg,
@@ -210,15 +233,27 @@ static const struct msi_domain_template pci_msi_template = {
 	},
 };
 
+static void pci_irq_shutdown_msix(struct irq_data *data)
+{
+	pci_msix_mask(irq_data_get_msi_desc(data));
+	cond_shutdown_parent(data);
+}
+
+static unsigned int pci_irq_startup_msix(struct irq_data *data)
+{
+	unsigned int ret = cond_startup_parent(data);
+
+	pci_msix_unmask(irq_data_get_msi_desc(data));
+	return ret;
+}
+
 static void pci_irq_mask_msix(struct irq_data *data)
 {
 	pci_msix_mask(irq_data_get_msi_desc(data));
-	cond_mask_parent(data);
 }
 
 static void pci_irq_unmask_msix(struct irq_data *data)
 {
-	cond_unmask_parent(data);
 	pci_msix_unmask(irq_data_get_msi_desc(data));
 }
 
@@ -234,6 +269,8 @@ EXPORT_SYMBOL_GPL(pci_msix_prepare_desc);
 static const struct msi_domain_template pci_msix_template = {
 	.chip = {
 		.name			= "PCI-MSIX",
+		.irq_startup		= pci_irq_startup_msix,
+		.irq_shutdown		= pci_irq_shutdown_msix,
 		.irq_mask		= pci_irq_mask_msix,
 		.irq_unmask		= pci_irq_unmask_msix,
 		.irq_write_msi_msg	= pci_msi_domain_write_msg,