Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This is entirely SoC clk drivers.

  The majority diff wise is for the new Rockchip and Qualcomm clk
  drivers which is mostly lines and lines of data structures to describe
  the clk hardware in these SoCs. Beyond those two, Renesas continues to
  incrementally add clks to their SoC drivers, causing them to show up
  higher in the diffstat this time because they added quite a few clks
  all over the place.

  Overall it is a semi-quiet release that has some new clk drivers and
  the usual fixes for clock data that was wrong or missing and
  non-critical cleanups that plug error paths or fix typos.

  New Drivers:
   - Qualcomm IPQ5424 Network Subsystem Clock Controller
   - Qualcomm SM8750 Video Clock Controller
   - Rockchip RV1126B and RK3506 clock drivers
   - i.MX8ULP SIM LPAV clock driver
   - Samsung ACPM (firmware interface) clock driver
   - Altera Agilex5 clock driver"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (117 commits)
  clk: keystone: fix compile testing
  clk: keystone: syscon-clk: fix regmap leak on probe failure
  clk: qcom: Mark camcc_sm7150_hws static
  clk: samsung: exynos-clkout: Assign .num before accessing .hws
  clk: rockchip: Add clock and reset driver for RK3506
  dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
  clk: actions: Fix discarding const qualifier by 'container_of' macro
  clk: spacemit: Set clk_hw_onecell_data::num before using flex array
  clk: visconti: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Remove definition of number of clocks
  clk: visconti: Do not define number of clocks in bindings
  clk: rockchip: Add clock controller for the RV1126B
  dt-bindings: clock, reset: Add support for rv1126b
  clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
  clk: qcom: x1e80100-dispcc: Add USB4 router link resets
  dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
  clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
  dt-bindings: clock: qcom: Add SM8750 video clock controller
  clk: qcom: branch: Extend invert logic for branch2 mem clocks
  ...

2 files changed, 56 insertions, 36 deletions

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 8d5ad0c1b27f..6e5d6deffa7d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -211,6 +211,7 @@ config RESET_PISTACHIO
 config RESET_POLARFIRE_SOC
 	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
 	depends on MCHP_CLK_MPFS
+	depends on MFD_SYSCON
 	select AUXILIARY_BUS
 	default MCHP_CLK_MPFS
 	help
diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c
index f6fa10e03ea8..8ffcc54ee6f6 100644
--- a/drivers/reset/reset-mpfs.c
+++ b/drivers/reset/reset-mpfs.c
@@ -9,11 +9,13 @@
 #include <linux/auxiliary_bus.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <linux/slab.h>
+#include <linux/regmap.h>
 #include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <dt-bindings/clock/microchip,mpfs-clock.h>
 #include <soc/microchip/mpfs.h>
 
@@ -27,11 +29,10 @@
 #define MPFS_SLEEP_MIN_US	100
 #define MPFS_SLEEP_MAX_US	200
 
-/* block concurrent access to the soft reset register */
-static DEFINE_SPINLOCK(mpfs_reset_lock);
+#define REG_SUBBLK_RESET_CR	0x88u
 
 struct mpfs_reset {
-	void __iomem *base;
+	struct regmap *regmap;
 	struct reset_controller_dev rcdev;
 };
 
@@ -46,41 +47,25 @@ static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcde
 static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
 {
 	struct mpfs_reset *rst = to_mpfs_reset(rcdev);
-	unsigned long flags;
-	u32 reg;
-
-	spin_lock_irqsave(&mpfs_reset_lock, flags);
-
-	reg = readl(rst->base);
-	reg |= BIT(id);
-	writel(reg, rst->base);
 
-	spin_unlock_irqrestore(&mpfs_reset_lock, flags);
+	return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
 
-	return 0;
 }
 
 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
 {
 	struct mpfs_reset *rst = to_mpfs_reset(rcdev);
-	unsigned long flags;
-	u32 reg;
-
-	spin_lock_irqsave(&mpfs_reset_lock, flags);
 
-	reg = readl(rst->base);
-	reg &= ~BIT(id);
-	writel(reg, rst->base);
+	return regmap_clear_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
 
-	spin_unlock_irqrestore(&mpfs_reset_lock, flags);
-
-	return 0;
 }
 
 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
 {
 	struct mpfs_reset *rst = to_mpfs_reset(rcdev);
-	u32 reg = readl(rst->base);
+	u32 reg;
+
+	regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, &reg);
 
 	/*
 	 * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
@@ -130,23 +115,58 @@ static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
 	return index - MPFS_PERIPH_OFFSET;
 }
 
-static int mpfs_reset_probe(struct auxiliary_device *adev,
-			    const struct auxiliary_device_id *id)
+static int mpfs_reset_mfd_probe(struct platform_device *pdev)
+{
+	struct reset_controller_dev *rcdev;
+	struct device *dev = &pdev->dev;
+	struct mpfs_reset *rst;
+
+	rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
+	if (!rst)
+		return -ENOMEM;
+
+	rcdev = &rst->rcdev;
+	rcdev->dev = dev;
+	rcdev->ops = &mpfs_reset_ops;
+
+	rcdev->of_node = pdev->dev.parent->of_node;
+	rcdev->of_reset_n_cells = 1;
+	rcdev->of_xlate = mpfs_reset_xlate;
+	rcdev->nr_resets = MPFS_NUM_RESETS;
+
+	rst->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
+	if (IS_ERR(rst->regmap))
+		return dev_err_probe(dev, PTR_ERR(rst->regmap),
+				     "Failed to find syscon regmap\n");
+
+	return devm_reset_controller_register(dev, rcdev);
+}
+
+static struct platform_driver mpfs_reset_mfd_driver = {
+	.probe = mpfs_reset_mfd_probe,
+	.driver = {
+		.name = "mpfs-reset",
+	},
+};
+module_platform_driver(mpfs_reset_mfd_driver);
+
+static int mpfs_reset_adev_probe(struct auxiliary_device *adev,
+				 const struct auxiliary_device_id *id)
 {
-	struct device *dev = &adev->dev;
 	struct reset_controller_dev *rcdev;
+	struct device *dev = &adev->dev;
 	struct mpfs_reset *rst;
 
 	rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
 	if (!rst)
 		return -ENOMEM;
 
-	rst->base = (void __iomem *)adev->dev.platform_data;
+	rst->regmap = (struct regmap *)adev->dev.platform_data;
 
 	rcdev = &rst->rcdev;
 	rcdev->dev = dev;
-	rcdev->dev->parent = dev->parent;
 	rcdev->ops = &mpfs_reset_ops;
+
 	rcdev->of_node = dev->parent->of_node;
 	rcdev->of_reset_n_cells = 1;
 	rcdev->of_xlate = mpfs_reset_xlate;
@@ -155,12 +175,11 @@ static int mpfs_reset_probe(struct auxiliary_device *adev,
 	return devm_reset_controller_register(dev, rcdev);
 }
 
-int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
+int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map)
 {
 	struct auxiliary_device *adev;
 
-	adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs",
-					    (__force void *)base);
+	adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs", (void *)map);
 	if (!adev)
 		return -ENODEV;
 
@@ -176,12 +195,12 @@ static const struct auxiliary_device_id mpfs_reset_ids[] = {
 };
 MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
 
-static struct auxiliary_driver mpfs_reset_driver = {
-	.probe		= mpfs_reset_probe,
+static struct auxiliary_driver mpfs_reset_aux_driver = {
+	.probe		= mpfs_reset_adev_probe,
 	.id_table	= mpfs_reset_ids,
 };
 
-module_auxiliary_driver(mpfs_reset_driver);
+module_auxiliary_driver(mpfs_reset_aux_driver);
 
 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");