Merge tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "There are lots of minor updates for driver subsystems managed through
  the soc tree (turris-omnia platform, cache driver, tee drivers,
  arm-cci, bus, memory) as well as soc vendor specific drivers
  (starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti,
  nvidia).

  The more notable changes are:

   - Larger updates for Qualcomm SoCs including support for SM8950
     (Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424

   - Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and
     MT8167 in existing drivers

   - Arm SCMI firmware driver support for ACPI PCC transport and module
     autoloading of protocol specific drivers

   - Apple crash log support for CrgA embedded controller"

* tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits)
  platform: cznic: turris-omnia-mcu: stop button emulation producers
  cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers
  soc: mpfs: use kref cleanup on probe failure
  arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms
  bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port()
  bus: arm-cci: Drop CPU node reference in cci_ace_init_ports()
  soc: fsl: dpio: Free the IRQ before releasing the I/O object
  soc: fsl: dpio: Fix cleanup on IRQ registration failure
  bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr
  bus: fsl-mc: drop the fwnode links of the dpmacs nodes
  soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms()
  soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get()
  firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7
  dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller
  dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC
  soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove
  ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
  firmware: qcom: tzmem: disable SHM bridge for SM7125 platform
  soc: qcom: ubwc: Add Kalambo UBWC config
  firmware: qcom: scm: Allow QSEECOM on Kalambo CRD
  ...

1 files changed, 167 insertions, 1 deletions

diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 2fad8b13a3b9..623848116b69 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -39,7 +39,8 @@
     defined(CONFIG_ARCH_TEGRA_186_SOC) || \
     defined(CONFIG_ARCH_TEGRA_194_SOC) || \
     defined(CONFIG_ARCH_TEGRA_234_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_241_SOC)
+    defined(CONFIG_ARCH_TEGRA_241_SOC) || \
+    defined(CONFIG_ARCH_TEGRA_264_SOC)
 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
 {
 	if (WARN_ON(!fuse->base))
@@ -802,3 +803,168 @@ const struct tegra_fuse_soc tegra241_fuse_soc = {
 	.soc_attr_group = &tegra194_soc_attr_group,
 };
 #endif
+
+#ifdef CONFIG_ARCH_TEGRA_264_SOC
+static const struct nvmem_keepout tegra264_fuse_keepouts[] = {
+	{ .start = 0x0019c, .end = 0x001a0 },
+	{ .start = 0x00308, .end = 0x00310 },
+	{ .start = 0x0032c, .end = 0x00334 },
+	{ .start = 0x00350, .end = 0x00354 },
+	{ .start = 0x00494, .end = 0x0049c },
+	{ .start = 0x0078c, .end = 0x00790 },
+	{ .start = 0x007a0, .end = 0x007a8 },
+	{ .start = 0x007dc, .end = 0x007e4 },
+	{ .start = 0x008d8, .end = 0x008dc },
+	{ .start = 0x0096c, .end = 0x00970 },
+	{ .start = 0x00974, .end = 0x0097c },
+	{ .start = 0x009f4, .end = 0x009f8 },
+	{ .start = 0x00a14, .end = 0x00a20 },
+	{ .start = 0x00a44, .end = 0x00a4c },
+	{ .start = 0x00a50, .end = 0x00a58 },
+	{ .start = 0x00a5c, .end = 0x00a64 },
+	{ .start = 0x00a68, .end = 0x00a70 },
+	{ .start = 0x00acc, .end = 0x00ad0 },
+	{ .start = 0x00b0c, .end = 0x00b18 },
+	{ .start = 0x00c80, .end = 0x00c8c },
+	{ .start = 0x00dac, .end = 0x00db4 },
+	{ .start = 0x00db8, .end = 0x00dbc },
+	{ .start = 0x00e0c, .end = 0x00e10 },
+	{ .start = 0x00fd0, .end = 0x01f00 },
+	{ .start = 0x01f1c, .end = 0x10064 },
+	{ .start = 0x10084, .end = 0x100a0 },
+	{ .start = 0x100a4, .end = 0x1019c },
+	{ .start = 0x101a0, .end = 0x101cc },
+	{ .start = 0x101d0, .end = 0x10308 },
+	{ .start = 0x10310, .end = 0x1055c },
+	{ .start = 0x1057c, .end = 0x106b0 },
+	{ .start = 0x106b4, .end = 0x11008 },
+	{ .start = 0x1100c, .end = 0x11018 },
+	{ .start = 0x11020, .end = 0x110b8 },
+	{ .start = 0x110c4, .end = 0x110c8 },
+	{ .start = 0x110e8, .end = 0x110ec },
+	{ .start = 0x110f0, .end = 0x11124 },
+	{ .start = 0x11128, .end = 0x11168 },
+	{ .start = 0x1116c, .end = 0x111b8 },
+	{ .start = 0x111bc, .end = 0x111e4 },
+	{ .start = 0x111e8, .end = 0x111ec },
+	{ .start = 0x111f0, .end = 0x1121c },
+	{ .start = 0x11250, .end = 0x1133c },
+	{ .start = 0x11340, .end = 0x113c8 },
+	{ .start = 0x113d0, .end = 0x11420 },
+	{ .start = 0x11430, .end = 0x11440 },
+	{ .start = 0x11444, .end = 0x11468 },
+	{ .start = 0x1146c, .end = 0x114a8 },
+	{ .start = 0x114ac, .end = 0x115cc },
+	{ .start = 0x115d0, .end = 0x115dc },
+	{ .start = 0x115e0, .end = 0x116b4 },
+	{ .start = 0x116bc, .end = 0x11740 },
+	{ .start = 0x11744, .end = 0x117b8 },
+	{ .start = 0x117bc, .end = 0x11810 },
+	{ .start = 0x11814, .end = 0x11850 },
+	{ .start = 0x11858, .end = 0x118a0 },
+	{ .start = 0x118ac, .end = 0x11b48 },
+	{ .start = 0x11b50, .end = 0x11b5c },
+	{ .start = 0x11b60, .end = 0x11bf8 },
+	{ .start = 0x11bfc, .end = 0x11c18 },
+	{ .start = 0x11c40, .end = 0x12000 },
+	{ .start = 0x12004, .end = 0x12010 },
+	{ .start = 0x12014, .end = 0x120fc },
+	{ .start = 0x1211c, .end = 0x12120 },
+	{ .start = 0x12124, .end = 0x12144 },
+	{ .start = 0x1214c, .end = 0x12300 },
+	{ .start = 0x12308, .end = 0x1236c },
+	{ .start = 0x12370, .end = 0x126ac },
+	{ .start = 0x126b0, .end = 0x12c60 },
+	{ .start = 0x12c64, .end = 0x12d94 },
+	{ .start = 0x12da4, .end = 0x13004 },
+	{ .start = 0x13008, .end = 0x1300c },
+	{ .start = 0x13010, .end = 0x13014 },
+	{ .start = 0x13018, .end = 0x13020 },
+	{ .start = 0x13064, .end = 0x13084 },
+	{ .start = 0x130a0, .end = 0x130a4 },
+	{ .start = 0x130b8, .end = 0x130c4 },
+	{ .start = 0x130c8, .end = 0x130e8 },
+	{ .start = 0x130ec, .end = 0x130f0 },
+	{ .start = 0x130fc, .end = 0x1311c },
+	{ .start = 0x13120, .end = 0x13128 },
+	{ .start = 0x13144, .end = 0x1314c },
+	{ .start = 0x13168, .end = 0x1316c },
+	{ .start = 0x1319c, .end = 0x131a0 },
+	{ .start = 0x131ac, .end = 0x131c0 },
+	{ .start = 0x131cc, .end = 0x131d0 },
+	{ .start = 0x131e4, .end = 0x131e8 },
+	{ .start = 0x131ec, .end = 0x131f0 },
+	{ .start = 0x1321c, .end = 0x13250 },
+	{ .start = 0x132f0, .end = 0x13310 },
+	{ .start = 0x1332c, .end = 0x13334 },
+	{ .start = 0x1333c, .end = 0x13344 },
+	{ .start = 0x13350, .end = 0x13354 },
+	{ .start = 0x1336c, .end = 0x13370 },
+	{ .start = 0x133ac, .end = 0x133b0 },
+	{ .start = 0x133c8, .end = 0x133d0 },
+	{ .start = 0x13420, .end = 0x13430 },
+	{ .start = 0x13440, .end = 0x13444 },
+	{ .start = 0x13468, .end = 0x13470 },
+	{ .start = 0x13494, .end = 0x1349c },
+	{ .start = 0x134a8, .end = 0x134ac },
+	{ .start = 0x13544, .end = 0x1354c },
+	{ .start = 0x1355c, .end = 0x1357c },
+	{ .start = 0x135cc, .end = 0x135e0 },
+	{ .start = 0x135e4, .end = 0x13608 },
+	{ .start = 0x1360c, .end = 0x13620 },
+	{ .start = 0x136ac, .end = 0x136bc },
+	{ .start = 0x136c0, .end = 0x136c8 },
+	{ .start = 0x13714, .end = 0x13718 },
+	{ .start = 0x13724, .end = 0x13728 },
+	{ .start = 0x1372c, .end = 0x13730 },
+	{ .start = 0x13734, .end = 0x1373c },
+	{ .start = 0x13740, .end = 0x13744 },
+	{ .start = 0x13754, .end = 0x13758 },
+	{ .start = 0x13760, .end = 0x13784 },
+	{ .start = 0x1378c, .end = 0x13790 },
+	{ .start = 0x137a0, .end = 0x137a8 },
+	{ .start = 0x137b8, .end = 0x137bc },
+	{ .start = 0x137dc, .end = 0x137e4 },
+	{ .start = 0x137ec, .end = 0x137f0 },
+	{ .start = 0x13800, .end = 0x13818 },
+	{ .start = 0x13820, .end = 0x13828 },
+	{ .start = 0x13830, .end = 0x13858 },
+	{ .start = 0x138a0, .end = 0x138b0 },
+	{ .start = 0x138d0, .end = 0x138dc },
+	{ .start = 0x1396c, .end = 0x13970 },
+	{ .start = 0x13974, .end = 0x1397c },
+	{ .start = 0x139f4, .end = 0x139f8 },
+	{ .start = 0x13a14, .end = 0x13a20 },
+	{ .start = 0x13a44, .end = 0x13a4c },
+	{ .start = 0x13a50, .end = 0x13a58 },
+	{ .start = 0x13a5c, .end = 0x13a64 },
+	{ .start = 0x13a68, .end = 0x13a70 },
+	{ .start = 0x13acc, .end = 0x13ad8 },
+	{ .start = 0x13b0c, .end = 0x13b18 },
+	{ .start = 0x13b48, .end = 0x13b50 },
+	{ .start = 0x13b5c, .end = 0x13b60 },
+	{ .start = 0x13bf8, .end = 0x13bfc },
+	{ .start = 0x13c18, .end = 0x13c40 },
+	{ .start = 0x13c60, .end = 0x13c64 },
+	{ .start = 0x13c74, .end = 0x13c8c },
+	{ .start = 0x13d94, .end = 0x13da4 },
+	{ .start = 0x13dac, .end = 0x13db4 },
+	{ .start = 0x13db8, .end = 0x13dbc },
+	{ .start = 0x13df4, .end = 0x13e04 },
+	{ .start = 0x13e0c, .end = 0x13e10 },
+};
+
+static const struct tegra_fuse_info tegra264_fuse_info = {
+	.read = tegra30_fuse_read,
+	.size = 0x13eb8,
+};
+
+const struct tegra_fuse_soc tegra264_fuse_soc = {
+	.init = tegra30_fuse_init,
+	.info = &tegra264_fuse_info,
+	.keepouts = tegra264_fuse_keepouts,
+	.num_keepouts = ARRAY_SIZE(tegra264_fuse_keepouts),
+	.soc_attr_group = &tegra194_soc_attr_group,
+	.clk_suspend_on = false,
+};
+#endif