diff options
| author | Abel Vesa <abel.vesa@linaro.org> | 2025-12-24 13:10:45 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-01-01 16:33:57 +0530 |
| commit | 2d472a675ced00397440caed78168db5fdecf3a3 (patch) | |
| tree | aeab1cebfce4195923ec7d4547d887b05ae47952 /drivers | |
| parent | 8f97b9b34f0d26339e8b0d26c2f466eeb188939b (diff) | |
phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count
On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx
registers. This hasn't been an issue so far on currently supported
platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9.
However, on the new upcoming Glymur platform, these are updated along
with the rest of the init sequence.
So update the size of the array holding the config to 13.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-2-4fcba75a6fa9@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-edp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 06a08c9ea0f7..f98fe83de42e 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,7 +32,7 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 -#define DP_AUX_CFG_SIZE 10 +#define DP_AUX_CFG_SIZE 13 #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 |