diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2010-12-03 17:53:35 -0600 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2010-12-03 17:55:35 -0600 |
| commit | 35f5c2725c403bebfb41a39dd02d85a42cec9f7f (patch) | |
| tree | c4057f05aa2a73f63d34141866a2f2f973cd6e9d /drivers | |
| parent | 421b2eb47e3bf15973939d2906b8f1ac7b15c1a9 (diff) | |
ENGR000135959: MX50: Relock PLL1 to 160MHz in LPAPM mode.
In LPAPM mode, DDR is sourced from 24MHz OSC. Since only ARM clock is
sourced from PLL1, relock it to 160MHz to save some power.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions