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authorPaolo Bonzini <pbonzini@redhat.com>2026-02-09 18:18:19 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2026-02-09 18:18:19 +0100
commit549006326978fbf66d9db2953cb1e4fb5487da65 (patch)
treedbf6a9a1c54c785dd3a2349a6f248bbfc863c426 /drivers
parentc14f646638ddf647e080d4755e9a008dc9db03e7 (diff)
parent6316366129d2885fae07c2774f4b7ae0a45fb55d (diff)
Merge tag 'kvmarm-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm64 updates for 7.0 - Add support for FEAT_IDST, allowing ID registers that are not implemented to be reported as a normal trap rather than as an UNDEF exception. - Add sanitisation of the VTCR_EL2 register, fixing a number of UXN/PXN/XN bugs in the process. - Full handling of RESx bits, instead of only RES0, and resulting in SCTLR_EL2 being added to the list of sanitised registers. - More pKVM fixes for features that are not supposed to be exposed to guests. - Make sure that MTE being disabled on the pKVM host doesn't give it the ability to attack the hypervisor. - Allow pKVM's host stage-2 mappings to use the Force Write Back version of the memory attributes by using the "pass-through' encoding. - Fix trapping of ICC_DIR_EL1 on GICv5 hosts emulating GICv3 for the guest. - Preliminary work for guest GICv5 support. - A bunch of debugfs fixes, removing pointless custom iterators stored in guest data structures. - A small set of FPSIMD cleanups. - Selftest fixes addressing the incorrect alignment of page allocation. - Other assorted low-impact fixes and spelling fixes.
Diffstat (limited to 'drivers')
-rw-r--r--drivers/irqchip/irq-gic-v5-irs.c2
-rw-r--r--drivers/irqchip/irq-gic-v5.c10
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c
index ce2732d649a3..eeeb40fb0eaa 100644
--- a/drivers/irqchip/irq-gic-v5-irs.c
+++ b/drivers/irqchip/irq-gic-v5-irs.c
@@ -743,6 +743,8 @@ static int __init gicv5_irs_init(struct device_node *node)
* be consistent across IRSes by the architecture.
*/
if (list_empty(&irs_nodes)) {
+ idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);
+ gicv5_global_data.virt_capable = !FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
irs_setup_pri_bits(idr);
diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
index 41ef286c4d78..3c86bbc05761 100644
--- a/drivers/irqchip/irq-gic-v5.c
+++ b/drivers/irqchip/irq-gic-v5.c
@@ -1064,6 +1064,16 @@ static struct gic_kvm_info gic_v5_kvm_info __initdata;
static void __init gic_of_setup_kvm_info(struct device_node *node)
{
+ /*
+ * If we don't have native GICv5 virtualisation support, then
+ * we also don't have FEAT_GCIE_LEGACY - the architecture
+ * forbids this combination.
+ */
+ if (!gicv5_global_data.virt_capable) {
+ pr_info("GIC implementation is not virtualization capable\n");
+ return;
+ }
+
gic_v5_kvm_info.type = GIC_V5;
/* GIC Virtual CPU interface maintenance interrupt */