diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2026-02-02 10:05:23 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-02-05 17:16:24 +0100 |
| commit | aacad391440ecc4f25e8d2db0d944a74fd874dd2 (patch) | |
| tree | 6c2c87805d1197c48c989eddeea283468f74ee5e /drivers | |
| parent | 8ccfe3ac901af9d4539f8ccc91b62f3a34a4ad9c (diff) | |
usb: phy: tegra: cosmetic fixes
Change TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC to its literal value instead of
using the BIT macro, as it is an enumeration. Correct the spelling in the
comment and rename uhsic_registers_shift to uhsic_registers_offset.
These changes are cosmetic and do not affect code behavior.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://patch.msgid.link/20260202080526.23487-2-clamor95@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/phy/phy-tegra-usb.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index effa767ec019..3a7a74f01d1c 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -48,7 +48,7 @@ #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) #define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22) -#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC BIT(2) +#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC 4 /* Bits of PORTSC1, which will get cleared by writing 1 into them */ #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) @@ -169,7 +169,7 @@ /* * Tegra20 has no UTMIP registers on PHY2 and UHSIC registers start from 0x800 * just where UTMIP registers should have been. This is the case only with Tegra20 - * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers shifter by 0x400 + * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers are shifted by 0x400 * to 0xc00, but register layout is preserved. */ #define UHSIC_PLL_CFG1 0x804 @@ -873,7 +873,7 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy) static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg) { void __iomem *base = phy->regs; - u32 shift = phy->soc_config->uhsic_registers_shift; + u32 shift = phy->soc_config->uhsic_registers_offset; return readl_relaxed(base + shift + reg); } @@ -881,7 +881,7 @@ static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg) static void tegra_hsic_writel(struct tegra_usb_phy *phy, u32 reg, u32 value) { void __iomem *base = phy->regs; - u32 shift = phy->soc_config->uhsic_registers_shift; + u32 shift = phy->soc_config->uhsic_registers_offset; writel_relaxed(value, base + shift + reg); } @@ -1469,7 +1469,7 @@ static const struct tegra_phy_soc_config tegra20_soc_config = { .requires_usbmode_setup = false, .requires_extra_tuning_parameters = false, .requires_pmc_ao_power_up = false, - .uhsic_registers_shift = 0, + .uhsic_registers_offset = 0, .uhsic_tx_rtune = 0, /* 40 ohm */ }; @@ -1479,7 +1479,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = { .requires_usbmode_setup = true, .requires_extra_tuning_parameters = true, .requires_pmc_ao_power_up = true, - .uhsic_registers_shift = 0x400, + .uhsic_registers_offset = 0x400, .uhsic_tx_rtune = 8, /* 50 ohm */ }; |