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authorMukul Joshi <mukul.joshi@amd.com>2025-03-27 17:17:06 -0400
committerAlex Deucher <alexander.deucher@amd.com>2025-12-08 14:25:34 -0500
commite3b8d8cc8c60db6c2be1251664da68b3e021a672 (patch)
treea13e35d8dbfa0661e819bb26a0640249fff848ce /drivers
parent3849efdc7888d537f09c3dcfaea4b3cd377a102e (diff)
drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0
Alignment mode in SHMEM config register is only a single bit value on GFX 12.1.0 instead of 2 bits in previous asics. Add a new enum and use the correct value of SHMEM alignment mode when programming the SHMEM config register. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c3
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c2
-rw-r--r--drivers/gpu/drm/amd/include/soc_v1_0_enum.h5
3 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 3080aecc8341..023a8a1114a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -52,9 +52,10 @@
MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");
+#define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
- (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
+ (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
index db7675c1498d..e4ec7190fea1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
@@ -24,7 +24,7 @@
#include "kfd_device_queue_manager.h"
#include "gc/gc_12_1_0_sh_mask.h"
-#include "soc24_enum.h"
+#include "soc_v1_0_enum.h"
static int update_qpd_v12_1(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
index 5a0963eaf3b9..2a910785334d 100644
--- a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
+++ b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
@@ -30,4 +30,9 @@ typedef enum MTYPE {
MTYPE_UC = 0x00000003,
} MTYPE;
+typedef enum SH_MEM_ALIGNMENT_MODE {
+ SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000001,
+} SH_MEM_ALIGNMENT_MODE;
+
#endif