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authorTony Luck <tony.luck@intel.com>2005-10-31 10:51:57 -0800
committerTony Luck <tony.luck@intel.com>2005-10-31 10:51:57 -0800
commitc7fb577e2a6cb04732541f2dc402bd46747f7558 (patch)
treedf3b1a1922ed13bfbcc45d08650c38beeb1a7bd1 /include/asm-ppc/cache.h
parent9cec58dc138d6fcad9f447a19c8ff69f6540e667 (diff)
parent581c1b14394aee60aff46ea67d05483261ed6527 (diff)
manual update from upstream:
Applied Al's change 06a544971fad0992fe8b92c5647538d573089dd4 to new location of swiotlb.c Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ppc/cache.h')
-rw-r--r--include/asm-ppc/cache.h13
1 files changed, 5 insertions, 8 deletions
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 38f2f1be4a87..7a157d0f4b5f 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -9,21 +9,18 @@
/* bytes per L1 cache line */
#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
-#define L1_CACHE_LINE_SIZE 16
-#define LG_L1_CACHE_LINE_SIZE 4
+#define L1_CACHE_SHIFT 4
#define MAX_COPY_PREFETCH 1
#elif defined(CONFIG_PPC64BRIDGE)
-#define L1_CACHE_LINE_SIZE 128
-#define LG_L1_CACHE_LINE_SIZE 7
+#define L1_CACHE_SHIFT 7
#define MAX_COPY_PREFETCH 1
#else
-#define L1_CACHE_LINE_SIZE 32
-#define LG_L1_CACHE_LINE_SIZE 5
+#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
#endif
-#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE
-#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */