diff options
| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2024-10-28 16:31:32 -0700 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2024-11-05 14:26:21 -0800 |
| commit | 3c1d5ced18db8a67251c8436cf9bdc061f972bdb (patch) | |
| tree | fe558c3b6c9d446f3ab6893b93e207f96703e772 /include/drm | |
| parent | ec70912110f449c9f1b866f4f75e10c056423426 (diff) | |
drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.
All MTL and ARL SKUs share the same GSC FW, but the newer platforms are
only supported in newer blobs. In particular, ARL-S is supported
starting from 102.0.10.1878 (which is already the minimum required
version for ARL in the code), while ARL-H and ARL-U are supported from
102.1.15.1926. Therefore, the driver needs to check which specific ARL
subplatform its running on when verifying that the GSC FW is new enough
for it.
Fixes: 2955ae8186c8 ("drm/i915: ARL requires a newer GSC firmware")
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028233132.149745-1-daniele.ceraolospurio@intel.com
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/intel/pciids.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h index 7632507af166..32480b5563db 100644 --- a/include/drm/intel/pciids.h +++ b/include/drm/intel/pciids.h @@ -765,13 +765,22 @@ INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) /* ARL */ -#define INTEL_ARL_IDS(MACRO__, ...) \ - MACRO__(0x7D41, ## __VA_ARGS__), \ +#define INTEL_ARL_H_IDS(MACRO__, ...) \ MACRO__(0x7D51, ## __VA_ARGS__), \ + MACRO__(0x7DD1, ## __VA_ARGS__) + +#define INTEL_ARL_U_IDS(MACRO__, ...) \ + MACRO__(0x7D41, ## __VA_ARGS__) \ + +#define INTEL_ARL_S_IDS(MACRO__, ...) \ MACRO__(0x7D67, ## __VA_ARGS__), \ - MACRO__(0x7DD1, ## __VA_ARGS__), \ MACRO__(0xB640, ## __VA_ARGS__) +#define INTEL_ARL_IDS(MACRO__, ...) \ + INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__) + /* MTL */ #define INTEL_MTL_IDS(MACRO__, ...) \ MACRO__(0x7D40, ## __VA_ARGS__), \ |