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authorThomas Zimmermann <tzimmermann@suse.de>2025-10-24 14:45:08 +0200
committerThomas Zimmermann <tzimmermann@suse.de>2025-10-24 14:45:08 +0200
commit5efbe8ff98aa56c2b537b03c97f2b2b87456acff (patch)
treefef9cca5d2163dc03627a23f751b47792e9dfd10 /include/drm
parent57fe8285dc4764171fa9eb1f153cae3bb313d6fc (diff)
parent098456f3141bf9e0c0d8973695ca38a03465ccd6 (diff)
Merge drm/drm-next into drm-misc-next
Backmerging to get fixes and features of v6.18-rc2. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_gpusvm.h4
-rw-r--r--include/drm/drm_gpuvm.h2
-rw-r--r--include/drm/intel/pciids.h16
3 files changed, 19 insertions, 3 deletions
diff --git a/include/drm/drm_gpusvm.h b/include/drm/drm_gpusvm.h
index b92faa9a26b2..632e100e6efb 100644
--- a/include/drm/drm_gpusvm.h
+++ b/include/drm/drm_gpusvm.h
@@ -235,6 +235,9 @@ struct drm_gpusvm {
* @read_only: operating on read-only memory
* @devmem_possible: possible to use device memory
* @devmem_only: use only device memory
+ * @allow_mixed: Allow mixed mappings in get pages. Mixing between system and
+ * single dpagemap is supported, mixing between multiple dpagemap
+ * is unsupported.
*
* Context that is DRM GPUSVM is operating in (i.e. user arguments).
*/
@@ -246,6 +249,7 @@ struct drm_gpusvm_ctx {
unsigned int read_only :1;
unsigned int devmem_possible :1;
unsigned int devmem_only :1;
+ unsigned int allow_mixed :1;
};
int drm_gpusvm_init(struct drm_gpusvm *gpusvm,
diff --git a/include/drm/drm_gpuvm.h b/include/drm/drm_gpuvm.h
index 8890ded1d907..476990e761f8 100644
--- a/include/drm/drm_gpuvm.h
+++ b/include/drm/drm_gpuvm.h
@@ -1078,7 +1078,7 @@ struct drm_gpuva_ops {
*/
struct drm_gpuvm_map_req {
/**
- * @op_map: struct drm_gpuva_op_map
+ * @map: struct drm_gpuva_op_map
*/
struct drm_gpuva_op_map map;
};
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index da6301a6fcea..9f095a99d6c9 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -849,7 +849,7 @@
MACRO__(0x64B0, ## __VA_ARGS__)
/* BMG */
-#define INTEL_BMG_IDS(MACRO__, ...) \
+#define INTEL_BMG_G21_IDS(MACRO__, ...) \
MACRO__(0xE202, ## __VA_ARGS__), \
MACRO__(0xE209, ## __VA_ARGS__), \
MACRO__(0xE20B, ## __VA_ARGS__), \
@@ -858,7 +858,10 @@
MACRO__(0xE210, ## __VA_ARGS__), \
MACRO__(0xE211, ## __VA_ARGS__), \
MACRO__(0xE212, ## __VA_ARGS__), \
- MACRO__(0xE216, ## __VA_ARGS__), \
+ MACRO__(0xE216, ## __VA_ARGS__)
+
+#define INTEL_BMG_IDS(MACRO__, ...) \
+ INTEL_BMG_G21_IDS(MACRO__, __VA_ARGS__), \
MACRO__(0xE220, ## __VA_ARGS__), \
MACRO__(0xE221, ## __VA_ARGS__), \
MACRO__(0xE222, ## __VA_ARGS__), \
@@ -881,4 +884,13 @@
MACRO__(0xFD80, ## __VA_ARGS__), \
MACRO__(0xFD81, ## __VA_ARGS__)
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+ MACRO__(0xD740, ## __VA_ARGS__), \
+ MACRO__(0xD741, ## __VA_ARGS__), \
+ MACRO__(0xD742, ## __VA_ARGS__), \
+ MACRO__(0xD743, ## __VA_ARGS__), \
+ MACRO__(0xD744, ## __VA_ARGS__), \
+ MACRO__(0xD745, ## __VA_ARGS__)
+
#endif /* __PCIIDS_H__ */