diff options
| author | Sricharan Ramabadhran <quic_srichara@quicinc.com> | 2025-08-11 14:39:51 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-08-11 10:05:20 -0500 |
| commit | c17ccefb611fdb346eef9be6bfbd0bfd04afa204 (patch) | |
| tree | 28277ea5f79c2042adeac3405deff388ed58565b /include/dt-bindings/interconnect | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'include/dt-bindings/interconnect')
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,ipq5424.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index a770356112ee..afd7e0683a24 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -21,4 +21,7 @@ #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_CPU 0 +#define SLAVE_L3 1 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ |