Merge tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlHEADmaster

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Add new generic callbacks to populate per-pin pin controllers
     creating groups and functions from the device tree building out
     pinctrl_generic_to_map() and move the Spacemit driver over to use
     this

   - Generic board-level pin control driver using the mux framework

  New pin controller drivers:

   - Amlogic (meson) A9 SoC

   - Aspeed AST2700 SoC0 and SoC1

   - nVidia Tegra264 and Tegra238

   - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM

   - Renesas RZ/G3L SoC

   - UltraRISC DP1000

  Improvements:

   - Handle pull up/pull down properly in the Renesas RZG2L driver

   - Fix up nVidia Tegra 234 DT bindings

   - Fix up pin definitions in the Qualcomm Eliza driver

   - Qualcomm PM8010 GPIO support in the PM8010

   - Qualcomm SM6115 EGPIO support in the SM6115

   - Switch Qualcomm LPASS LPI drivers to use runtime PM for power
     management

   - Clean up the Qualcomm Kconfig business a bit to include the
     necessary drivers for each subarch

   - Fix output glitch in the Amlogic (meson) A4 pin controller

   - Move the Airoha driver from the Mediatek directory to its own
     directory. It is too different from other Mediatek hardware

   - A slew of fixes to the Airoha AN7581 and AN7583 drivers"

* tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits)
  pinctrl: Export pinctrl_get_group_selector()
  pinctrl: Match DT helper types
  pinctrl: qcom: Register functions before enabling pinctrl
  pinctrl: meson: amlogic-a4: use nolock get range
  pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver
  dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller
  pinctrl: qcom: Remove unused macro definitions
  pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA
  pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA
  pinctrl: tegra238: add missing AON pin groups
  dt-bindings: pinctrl: tegra238: add missing AON pin groups
  pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function
  pinctrl: airoha: an7583: fix phy1_led1 pin function
  pinctrl: airoha: an7583: add missed gpio22 pin group
  pinctrl: airoha: an7583: fix gpio21 pin group
  pinctrl: airoha: fix pwm pin function for an7581 and an7583
  pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function
  pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function
  pinctrl: airoha: an7583: fix misprint in gpio19 pinconf
  pinctrl: airoha: an7581: fix misprint in gpio19 pinconf
  ...

1 files changed, 39 insertions, 0 deletions

diff --git a/include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h b/include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h
new file mode 100644
index 000000000000..c65278c8103d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef __DTS_MT6392_PINFUNC_H
+#define __DTS_MT6392_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT6392_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT6392_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1)
+#define MT6392_PIN_0_INT__FUNC_TEST_CK2 (MTK_PIN_NO(0) | 5)
+#define MT6392_PIN_0_INT__FUNC_TEST_IN1 (MTK_PIN_NO(0) | 6)
+#define MT6392_PIN_0_INT__FUNC_TEST_OUT1 (MTK_PIN_NO(0) | 7)
+
+#define MT6392_PIN_1_SRCLKEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT6392_PIN_1_SRCLKEN__FUNC_SRCLKEN (MTK_PIN_NO(1) | 1)
+#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_CK0 (MTK_PIN_NO(1) | 5)
+#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_IN2 (MTK_PIN_NO(1) | 6)
+#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_OUT2 (MTK_PIN_NO(1) | 7)
+
+#define MT6392_PIN_2_RTC_32K1V8__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT6392_PIN_2_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(2) | 1)
+#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_CK1 (MTK_PIN_NO(2) | 5)
+#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_IN3 (MTK_PIN_NO(2) | 6)
+#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_OUT3 (MTK_PIN_NO(2) | 7)
+
+#define MT6392_PIN_3_SPI_CLK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT6392_PIN_3_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(3) | 1)
+
+#define MT6392_PIN_4_SPI_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT6392_PIN_4_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(4) | 1)
+
+#define MT6392_PIN_5_SPI_MOSI__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT6392_PIN_5_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(5) | 1)
+
+#define MT6392_PIN_6_SPI_MISO__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT6392_PIN_6_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(6) | 1)
+#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_IN4 (MTK_PIN_NO(6) | 6)
+#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_OUT4 (MTK_PIN_NO(6) | 7)
+
+#endif /* __DTS_MT6392_PINFUNC_H */