diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2019-08-22 20:03:48 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:28:39 +0800 |
| commit | 17f458d0a4373b8c6d824b343b1b3dad9532c2f3 (patch) | |
| tree | 662ede92eb9fa1ed0e7a6154ed3bcaeea9a2fbab /include/dt-bindings | |
| parent | e9c584db53f38183c175f1b44e72d38c794fd948 (diff) | |
clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transfering the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx7ulp-clock.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 6f66f9005c81..f8d34fb4378f 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -49,15 +49,14 @@ #define IMX7ULP_CLK_NIC1_DIV 36 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 +#define IMX7ULP_CLK_SIRC 39 +#define IMX7ULP_CLK_SOSC_BUS_CLK 40 +#define IMX7ULP_CLK_FIRC_BUS_CLK 41 +#define IMX7ULP_CLK_SPLL_BUS_CLK 42 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 43 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 44 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_SCG1_END 45 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 |