diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-12-24 16:50:46 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-01-08 10:07:47 +0100 |
| commit | 481b64376c3fb72557725acf2f4fbc4f73bc3188 (patch) | |
| tree | cad8a385faffa8431059536aa447eaa2f53dcbe0 /include/dt-bindings | |
| parent | 7c0b8360a4e2892bc1748aca77c0825af82f3dcd (diff) | |
dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID
Add PCLKCAN ID for CANFD to both R9A09G077 and R9A09G087 SoCs.
This definition is required for describing CANFD device in DT.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224165049.3384870-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 9eaedca6a616..c4863e444458 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G077_ETCLKE 21 #define R9A09G077_XSPI_CLK0 22 #define R9A09G077_XSPI_CLK1 23 +#define R9A09G077_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 606468ac49a4..0d53f1e65077 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G087_ETCLKE 21 #define R9A09G087_XSPI_CLK0 22 #define R9A09G087_XSPI_CLK1 23 +#define R9A09G087_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ |