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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-07-31 18:52:16 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2025-07-31 18:52:16 +0200
commit9cf9db888f387844e063efc6296e9fa5c042995e (patch)
tree6c0cea7ecc9f06c93194ec80551e98e07871e3d7 /include/linux/cpu.h
parent3dd8aa0ef78e4941f4b915d317616c03d08e31b2 (diff)
parentfb2fae70e7e985c4acb1ad96110d8b98bb64a87c (diff)
Merge tag 'nand/for-6.17' into mtd/next
* Raw NAND changes: Various controller drivers received minor fixes like DMA mapping checks, better timing derivations or bitflip statistics. It has also been discovered that some Hynix NAND flashes were not supporting read-retries, which is not properly supported. * SPI NAND changes: In order to support high-speed modes, certain chips need extra configuration like adding more dummy cycles. This is now possible, especially on Winbond chips. Aside from that, Gigadevice gets support for a new chip (GD5F1GM9). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'include/linux/cpu.h')
-rw-r--r--include/linux/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index e6089abc28e2..96a3a0d6a60e 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -120,6 +120,7 @@ extern void cpu_maps_update_begin(void);
extern void cpu_maps_update_done(void);
int bringup_hibernate_cpu(unsigned int sleep_cpu);
void bringup_nonboot_cpus(unsigned int max_cpus);
+int arch_cpu_rescan_dead_smt_siblings(void);
#else /* CONFIG_SMP */
#define cpuhp_tasks_frozen 0
@@ -134,6 +135,8 @@ static inline void cpu_maps_update_done(void)
static inline int add_cpu(unsigned int cpu) { return 0;}
+static inline int arch_cpu_rescan_dead_smt_siblings(void) { return 0; }
+
#endif /* CONFIG_SMP */
extern const struct bus_type cpu_subsys;