net: dsa: realtek: rtl8365mb: add EEE support

Add EEE support on the integrated-PHY ports, controllable per port via
ethtool.

The integrated PHYs have no MMD registers; their EEE registers live in the
switch's OCP space. phylib accesses EEE as MMD registers, so add
phy_{read,write}_c45 realtek_ops that map those MMD accesses onto their OCP
addresses, wired as the user MII bus C45 handlers when the chip provides
them (rtl8366rb etc. unaffected).

The hardware manages LPI on its own, so advertise EEE to phylink with no-op
mac_{en,dis}able_tx_lpi callbacks. The integrated PHYs advertise EEE by
default -- advertised, not necessarily active, since LPI is entered only
once both link partners advertise it and the link idles. No strap pin
selects EEE in the vendor register map, so on the hardware tested this
default is uniform and not board-specific, and marking EEE enabled by
default in phylink matches the PHY's power-on advertisement. Only the
integrated-PHY ports support EEE; the external RGMII ports do not. The LPI
timer is a single global per-speed register, so .set_mac_eee rejects the
per-port TX LPI knobs rather than silently ignoring them.

This assumes the integrated PHYs advertise EEE out of reset regardless of
board configuration; should a strap or other non-kernel mechanism disable
EEE advertisement on some board or chip in the family, enabling it by
default here would change that default behaviour.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://patch.msgid.link/20260918091722.3270534-4-o.rempel@pengutronix.de
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

0 files changed, 0 insertions, 0 deletions