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| author | Thomas Gleixner <tglx@linutronix.de> | 2008-09-06 03:06:08 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-10-08 19:44:43 -0700 |
| commit | 22e4330618d27748cc69b62d3c96223bcefe6c6c (patch) | |
| tree | 8b2c2f4e0f15b8fb75a284093d2ccfb3db4e4b1e /include/linux/mbcache.h | |
| parent | 59ff733c6b6ef547bb09a9902020750dfbb2200f (diff) | |
x86: HPET: read back compare register before reading counter
commit 72d43d9bc9210d24d09202eaf219eac09e17b339 upstream
After fixing the u32 thinko I sill had occasional hickups on ATI chipsets
with small deltas. There seems to be a delay between writing the compare
register and the transffer to the internal register which triggers the
interrupt. Reading back the value makes sure, that it hit the internal
match register befor we compare against the counter value.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/mbcache.h')
0 files changed, 0 insertions, 0 deletions