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| author | Jerome Brunet <jbrunet@baylibre.com> | 2024-07-29 16:32:02 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-07-29 16:32:02 +0200 |
| commit | 66e72a01b60ae6950ddbb3585fdc1424d303e14b (patch) | |
| tree | 05789274ef25cb5d08b99d1797e7760047469685 /include/linux/platform_data/tmio.h | |
| parent | 3d0e8b6edd6b08f72e07e1230f371f6ca93531e4 (diff) | |
| parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) | |
Merge tag 'v6.11-rc1' into clk-meson-next
Linux 6.11-rc1
Diffstat (limited to 'include/linux/platform_data/tmio.h')
| -rw-r--r-- | include/linux/platform_data/tmio.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h new file mode 100644 index 000000000000..b060124ba1ae --- /dev/null +++ b/include/linux/platform_data/tmio.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef MFD_TMIO_H +#define MFD_TMIO_H + +#include <linux/platform_device.h> +#include <linux/types.h> + +/* TMIO MMC platform flags */ + +/* + * Some controllers can support a 2-byte block size when the bus width is + * configured in 4-bit mode. + */ +#define TMIO_MMC_BLKSZ_2BYTES BIT(1) + +/* Some controllers can support SDIO IRQ signalling */ +#define TMIO_MMC_SDIO_IRQ BIT(2) + +/* Some features are only available or tested on R-Car Gen2 or later */ +#define TMIO_MMC_MIN_RCAR2 BIT(3) + +/* + * Some controllers require waiting for the SD bus to become idle before + * writing to some registers. + */ +#define TMIO_MMC_HAS_IDLE_WAIT BIT(4) + +/* + * Use the busy timeout feature. Probably all TMIO versions support it. Yet, + * we don't have documentation for old variants, so we enable only known good + * variants with this flag. Can be removed once all variants are known good. + */ +#define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5) + +/* Some controllers have CMD12 automatically issue/non-issue register */ +#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) + +/* Controller has some SDIO status bits which must be 1 */ +#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) + +/* Some controllers have a 32-bit wide data port register */ +#define TMIO_MMC_32BIT_DATA_PORT BIT(9) + +/* Some controllers allows to set SDx actual clock */ +#define TMIO_MMC_CLK_ACTUAL BIT(10) + +/* Some controllers have a CBSY bit */ +#define TMIO_MMC_HAVE_CBSY BIT(11) + +struct tmio_mmc_data { + void *chan_priv_tx; + void *chan_priv_rx; + unsigned int hclk; + unsigned long capabilities; + unsigned long capabilities2; + unsigned long flags; + u32 ocr_mask; /* available voltages */ + dma_addr_t dma_rx_offset; + unsigned int max_blk_count; + unsigned short max_segs; +}; +#endif |
