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authorLinus Torvalds <torvalds@linux-foundation.org>2025-05-31 07:53:30 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2025-05-31 07:53:30 -0700
commit297d9111e9fcf47dd1dcc6f79bba915f35378d01 (patch)
tree4763591ce5abc4a1dd7ebc3398affa5b3077248d /include/linux/soc
parent9d49da438819c5dd82840eb63d929edbdccb80d8 (diff)
parent5963edd98a2159f2114b08e402a7341c1e7dd293 (diff)
Merge tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann: "Updates are across the usual driver subsystems with SoC specific drivers: - added soc specicific drivers for sophgo cv1800 and sg2044, qualcomm sm8750, and amlogic c3 and s4 chips. - cache controller updates for sifive chips, plus binding changes for other cache descriptions. - memory controller drivers for mediatek mt6893, stm32 and cleanups for a few more drivers - reset controller drivers for T-Head TH1502, Sophgo sg2044 and Renesas RZ/V2H(P) - SCMI firmware updates to better deal with buggy firmware, plus better support for Qualcomm X1E and NXP i.MX specific interfaces - a new platform driver for the crypto firmware on Cznic Turris Omnia/MOX - cleanups for the TEE firmware subsystem and amdtee driver - minor updates and fixes for freescale/nxp, qualcomm, google, aspeed, wondermedia, ti, nxp, renesas, hisilicon, mediatek, broadcom and samsung SoCs" * tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (133 commits) soc: aspeed: Add NULL check in aspeed_lpc_enable_snoop() soc: aspeed: lpc: Fix impossible judgment condition ARM: aspeed: Don't select SRAM docs: firmware: qcom_scm: Fix kernel-doc warning soc: fsl: qe: Consolidate chained IRQ handler install/remove firmware: qcom: scm: Allow QSEECOM for HP EliteBook Ultra G1q dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018 dt-bindings: cache: add QiLai compatible to ax45mp memory: stm32_omm: Fix error handling in stm32_omm_disable_child() dt-bindings: cache: Convert marvell,tauros2-cache to DT schema dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema soc: samsung: exynos-pmu: enable CPU hotplug support for gs101 MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation bus: fsl-mc: Use strscpy() instead of strscpy_pad() soc: fsl: qbman: Remove const from portal->cgrs allocation type bus: fsl_mc: Fix driver_managed_dma check bus: fsl-mc: increase MC_CMD_COMPLETION_TIMEOUT_MS value bus: fsl-mc: drop useless cleanup ...
Diffstat (limited to 'include/linux/soc')
-rw-r--r--include/linux/soc/qcom/llcc-qcom.h8
-rw-r--r--include/linux/soc/samsung/exynos-regs-pmu.h11
2 files changed, 19 insertions, 0 deletions
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 8e5d78fb4847..7a69210a250c 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -24,6 +24,7 @@
#define LLCC_CMPTDMA 15
#define LLCC_DISP 16
#define LLCC_VIDFW 17
+#define LLCC_CAMFW 18
#define LLCC_MDMHPFX 20
#define LLCC_MDMPNG 21
#define LLCC_AUDHW 22
@@ -67,6 +68,13 @@
#define LLCC_EVCS_LEFT 67
#define LLCC_EVCS_RIGHT 68
#define LLCC_SPAD 69
+#define LLCC_VIDDEC 70
+#define LLCC_CAMOFE 71
+#define LLCC_CAMRTIP 72
+#define LLCC_CAMSRTIP 73
+#define LLCC_CAMRTRF 74
+#define LLCC_CAMSRTRF 75
+#define LLCC_CPUSSMPAM 89
/**
* struct llcc_slice_desc - Cache slice descriptor
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index ce1a3790d6fb..0d5a17ea8fb8 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -658,9 +658,20 @@
#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
/* For Tensor GS101 */
+/* PMU ALIVE */
#define GS101_SYSIP_DAT0 (0x810)
+#define GS101_CPU0_INFORM (0x860)
+#define GS101_CPU_INFORM(cpu) \
+ (GS101_CPU0_INFORM + (cpu*4))
#define GS101_SYSTEM_CONFIGURATION (0x3A00)
#define GS101_PHY_CTRL_USB20 (0x3EB0)
#define GS101_PHY_CTRL_USBDP (0x3EB4)
+/* PMU INTR GEN */
+#define GS101_GRP1_INTR_BID_UPEND (0x0108)
+#define GS101_GRP1_INTR_BID_CLEAR (0x010c)
+#define GS101_GRP2_INTR_BID_ENABLE (0x0200)
+#define GS101_GRP2_INTR_BID_UPEND (0x0208)
+#define GS101_GRP2_INTR_BID_CLEAR (0x020c)
+
#endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */