diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2026-02-02 10:05:26 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-02-05 17:16:24 +0100 |
| commit | e5b250214aa402e079de566e10f6e01223fd26bd (patch) | |
| tree | 4f0f18cbbaf5af164e06e3efb124c61a937cb97c /include/linux/usb | |
| parent | 8dc7ab65bd15e3c774f60ca073158bcb9a26ee5b (diff) | |
usb: phy: tegra: parametrize PORTSC1 register offset
The PORTSC1 register has a different offset in Tegra20 compared to
Tegra30+, yet they share a crucial set of registers required for HSIC
functionality. Reflect this register offset change in the SoC config.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://patch.msgid.link/20260202080526.23487-5-clamor95@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/usb')
| -rw-r--r-- | include/linux/usb/tegra_usb_phy.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index 7209b7731c29..6343f88df5de 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -27,6 +27,7 @@ struct gpio_desc; * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver * uhsic_pts_value: parallel transceiver select enumeration value + * portsc1_offset: register offset of PORTSC1 */ struct tegra_phy_soc_config { @@ -38,6 +39,7 @@ struct tegra_phy_soc_config { u32 uhsic_registers_offset; u32 uhsic_tx_rtune; u32 uhsic_pts_value; + u32 portsc1_offset; }; struct tegra_utmip_config { |