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authorAya Levin <ayal@nvidia.com>2021-04-04 10:50:50 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-04-14 08:42:11 +0200
commit1312f11eb33de7014b36551dc415be22553be66c (patch)
tree00052cb40f758016ece1a9d8469e26d20b7db3f8 /include/linux
parentf92faf0bdd25897bf6f041939d4beada1ff758e3 (diff)
net/mlx5: Fix PPLM register mapping
[ Upstream commit ce28f0fd670ddffcd564ce7119bdefbaf08f02d3 ] Add reserved mapping to cover all the register in order to avoid setting arbitrary values to newer FW which implements the reserved fields. Fixes: a58837f52d43 ("net/mlx5e: Expose FEC feilds and related capability bit") Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 19c1cb214953..4b3b2bf83720 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -8719,6 +8719,8 @@ struct mlx5_ifc_pplm_reg_bits {
u8 fec_override_admin_100g_2x[0x10];
u8 fec_override_admin_50g_1x[0x10];
+
+ u8 reserved_at_140[0x140];
};
struct mlx5_ifc_ppcnt_reg_bits {