diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2023-02-07 11:12:24 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-02-07 11:12:24 -0800 |
| commit | 5485eb955994a238eafd08d9266005b1c9ac7991 (patch) | |
| tree | fad2a31e1f9340de6aecbec16fa18509409ff5d1 /include/linux | |
| parent | 711442e29f16f0d39dd0e2460c9baacfccb9d5a7 (diff) | |
| parent | 623c0751336e4035ab0047f2c152a02bd26b612b (diff) | |
Merge branch 'for-6.3/cxl' into cxl/next
Merge the general CXL updates with fixes targeting v6.2-rc for v6.3.
Resolve a conflict with the fix and move of cxl_report_and_clear() from
pci.c to core/pci.c.
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index adffd65e84b4..22319ea71ab0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -578,6 +578,7 @@ struct pci_host_bridge { unsigned int native_pme:1; /* OS may use PCIe PME */ unsigned int native_ltr:1; /* OS may use PCIe LTR */ unsigned int native_dpc:1; /* OS may use PCIe DPC */ + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ unsigned int preserve_config:1; /* Preserve FW resource setup */ unsigned int size_windows:1; /* Enable root bus sizing */ unsigned int msi_domain:1; /* Bridge wants MSI domain */ |