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authorManivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>2026-01-02 21:04:48 +0530
committerBjorn Helgaas <bhelgaas@google.com>2026-02-06 16:54:12 -0600
commit8f05a5f6745ccc9ff784736608c5a38edb09acc8 (patch)
tree4603224c1d525af9c9371470c25244a7bf492845 /include/linux
parentc41e2fb67e26b04d919257875fa954aa5f6e392e (diff)
PCI: Cache ACS Capabilities register
The ACS Capability register is read-only. Cache it to allow quirks to override it and to avoid re-reading it. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Link: https://patch.msgid.link/20260102-pci_acs-v3-2-72280b94d288@oss.qualcomm.com
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/pci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 864775651c6f..6195e040b29c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -558,6 +558,7 @@ struct pci_dev {
struct pci_tsm *tsm; /* TSM operation state */
#endif
u16 acs_cap; /* ACS Capability offset */
+ u16 acs_capabilities; /* ACS Capabilities */
u8 supported_speeds; /* Supported Link Speeds Vector */
phys_addr_t rom; /* Physical address if not from BAR */
size_t romlen; /* Length if not from BAR */