diff options
| author | Fugang Duan <B38611@freescale.com> | 2012-02-08 11:39:25 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:22:15 +0800 |
| commit | 9097d4e27b4a1afc64e3f8479ce68387ed9b1755 (patch) | |
| tree | d7cad49bd1d7728514bd9ca5c2ec0309dce3aa16 /include/linux | |
| parent | f8be5ffb1f330fe29bbaf009eac9bf2d0619dc25 (diff) | |
ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.
Default use RMII 50MHz clock for ts_clk.
Test result:
Enet work fine at 100/1000Mbps in TO1.1 and Rigel.
IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz
timestamp clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions