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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-04-03 11:19:24 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2025-04-29 11:05:34 +0200
commitac3a4b17e03b079c00eb61456364bcdbf65f3436 (patch)
tree2cc7f861c2370c8c0fb41cee78070ba7993972f8 /include/linux
parent07cdbae7f84190983f9b07133ce5b6f2634c95cd (diff)
mtd: spinand: Use more specific naming for the (quad) program load op
SPI operations have been initially described through macros implicitly implying the use of a single SPI SDR bus. Macros for supporting dual and quad I/O transfers have been added on top, generally inspired by vendor naming, followed by DTR operations. Soon we might see octal and even octal DTR operations as well (including the opcode byte). Let's clarify what the macro really means by describing the expected bus topology in the (quad) program load macro name. While at modifying it, better add the missing_ OP suffix to align with all the other macros of the same kind. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mtd/spinand.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index d1cc2cdbd4a1..c70d17e0b308 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -182,7 +182,7 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT(len, buf, 1))
-#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
+#define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
SPI_MEM_OP_ADDR(2, addr, 1), \
SPI_MEM_OP_NO_DUMMY, \