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authorAlexei Lazar <alazar@nvidia.com>2026-03-09 11:34:27 +0200
committerLeon Romanovsky <leon@kernel.org>2026-03-16 16:23:00 -0400
commitf8e761655997cc0ee434fb5f35570d2e93d3a707 (patch)
tree1dff795e03f97d5b5eddf1246dbe914e1368f522 /include/linux
parent385a06f74ff7a03e3fb0b15fb87cfeb052d75073 (diff)
net/mlx5: Add IFC bits for shared headroom pool PBMC support
Add hardware interface definitions for shared headroom pool (SHP) in port buffer management: - shp_pbmc_pbsr_support: capability bit in PCAM enhanced features indicating device support for shared headroom pool in PBMC/PBSR. - shared_headroom_pool: buffer entry in PBMC register (pbmc_reg_bits) for the shared headroom pool configuration, reusing the bufferx layout; reduce trailing reserved region accordingly. Signed-off-by: Alexei Lazar <alazar@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/20260309093435.1850724-2-tariqt@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index a3948b36820d..a76c54bf1927 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -10845,7 +10845,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits {
u8 fec_200G_per_lane_in_pplm[0x1];
u8 reserved_at_1e[0x2a];
u8 fec_100G_per_lane_in_pplm[0x1];
- u8 reserved_at_49[0xa];
+ u8 reserved_at_49[0x2];
+ u8 shp_pbmc_pbsr_support[0x1];
+ u8 reserved_at_4c[0x7];
u8 buffer_ownership[0x1];
u8 resereved_at_54[0x14];
u8 fec_50G_per_lane_in_pplm[0x1];
@@ -12090,8 +12092,9 @@ struct mlx5_ifc_pbmc_reg_bits {
u8 port_buffer_size[0x10];
struct mlx5_ifc_bufferx_reg_bits buffer[10];
+ struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool;
- u8 reserved_at_2e0[0x80];
+ u8 reserved_at_320[0x40];
};
struct mlx5_ifc_sbpr_reg_bits {